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參數(shù)資料
| 型號： | IDT72T51556L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 36 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 639K |
| 代理商： | IDT72T51556L6BBI |
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12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 59-62 and Figures 36-38.
TRST
(2)
(Continued)
WADEN
(P4)
JTAG Reset
LVTTL
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces
TRST
HIGH if left unconnected.
HSTL-LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
INPUT
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
that a write queue selection cannot be made, (WADEN must NOT go active) until programmng of the part
has been completed and
SENO
has gone LOW.
HSTL-LVTTL When enabled by
WEN
, the rising edge of WCLK writes data into the selected Queue via the input
INPUT
bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of
WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also
select the flag quadrant to be placed on the
PAF
n bus during direct flag operation. During polled flag
operation the
PAF
n bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK.
The
PAF
n,
PAF
and
FF
outputs are all synchronized to WCLK. During device expansion the FXO and
FXI signals are based on WCLK. The WCLK must be continuous and free-running.
HSTL-LVTTL The
WEN
input enables write operations to a selected Queue based on a rising edge of WCLK. A
INPUT
queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless
of the state of
WEN
. Data present on Din can be written to a newly selected queue on the second WCLK
cycle after queue selection provided that
WEN
is LOW. A write enable is not required to cycle the
PAF
n
bus (in polled mode) or to select the
PAF
n quadrant , (in direct mode).
HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
INPUT
first function of WRADD is to select a Queue to be written to. The least significant 5 bits of the bus,
WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant
3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present
on the WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that
data present on the Din bus can be written into the previously selected queue on this WCLK edge and
on the next rising WCLK also, providing that
WEN
is LOW). Two WCLK rising edges after write queue
select, data can be written into the newly selected queue.
The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the
PAF
n
bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant
of a device to be placed on the
PAF
n bus. The most significant 3 bits, WRADD[7:5] are again used to
select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits
WRADD[4:2] are dont care during quadrant selection. The quadrant address present on the WRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be
written into the previously selected queue on this WCLK edge). Please refer to Table 1 for details on the
WRADD bus.
Power
These are V
CC
power supply pins and must all be connected to a +2.5V supply rail.
Write Address
Enable
WCLK
(T7)
Write Clock
WEN
(T6)
Write Enable
WRADD
[7:0]
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
Write Address
Bus
V
CC
(See pg. 13)
V
DDQ
(See pg. 13)
+2.5V Supply
O/P Rail Voltage
Power
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
These are Ground pins and must all be connected to the GND supply rail.
GND
(See pg. 13)
Vref
(K3)
Ground Pin
Ground
Reference
Voltage
HSTL
INPUT
This is a Voltage Reference input and must be connected to a voltage level determned fromthe table
"Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
Symbol &
Pin No.
Name
I/O TYPE
Description
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