參數(shù)資料
型號(hào): IDT74FCT16260ATPA8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封裝: TSSOP-56
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 67K
代理商: IDT74FCT16260ATPA8
1
IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIALTEMPERATURERANGE
JANUARY 2002
IDT74FCT16260AT/CT/ET
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
DESCRIPTION:
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit latched
busmultiplexers/transceiversforuseinhigh-speedmicroprocessorapplica-
tions. TheseBusExchangerssupportmemoryinterleavingwithlatchedoutputs
on the B ports and address multiplexing with latched inputs on the B ports.
TheTri-PortBusExchangerhasthree12-bitports. Datamaybetransferred
betweentheAportandeither/bothoftheBports. Thelatchenable(LE1B,LE2B,
LEA1BandLEA2B)inputscontroldatastorage. Whenalatch-enableinputis
high,thelatchistransparent. Whenalatch-enableinputislow,thedataatthe
inputislatchedandremainslatcheduntilthelatchenableinputisreturnedhigh.
Independent output enables (OE1B and OE2B) allow reading from one port
while writing to the other port.
TheFCT16260Tisideallysuitedfordrivinghighcapacitanceloadsandlow
impedancebackplanes. Theoutputbuffersaredesignedwithpoweroffdisable
capability to allow "live insertion" of boards when used as backplane drivers.
A-1B
LATCH
LEA1B
LE1B
LE2B
12
M
U
X
12
OE1B
12
A1:12
1B-A
LATCH
1B1:12
12
2B-A
LATCH
12
A-2B
LATCH
LEA2B
12
2B1:12
OE2B
OEA
SEL
1
0
29
30
2
28
1
27
55
56
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5431/3
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage
≤≤≤≤≤1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 5V ±10%
High drive outputs (–32mA IOH, 64mA IOL)
Power off disable outputs permit “l(fā)ive insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
Power off disable outputs permit “l(fā)ive insertion”
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
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