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參數(shù)資料
| 型號： | IDT74FCT162952ATPAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 77K |
| 代理商： | IDT74FCT162952ATPAG |
5
IDT74FCT162952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
FCT162952AT
FCT162952CT
FCT162952ET
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
PropagationDelay
CL = 50pF
2
10
2
6.3
1.5
3.7
ns
tPHL
xCLKAB, xCLKBA to xBx, xAx
RL = 500
tPZH
OutputEnableTime
1.5
10.5
1.5
7
1.5
4.4
ns
tPZL
xOEBA, xOEAB to xAx, xBx
tPHZ
OutputDisableTime
1.5
10
1.5
6.5
1.5
3.6
ns
tPLZ
xOEBA, xOEAB to xAx, xBx
tSU
Set-up Time, HIGH or LOW
2.5
—
2.5
—
1.5
—
ns
xAx, xBx to xCLKAB, xCLKBA
tH
Hold Time HIGH or LOW
2
—
1.5
—
0
—
ns
xAx, xBx to xCLKAB, xCLKBA
tSU
Set-up Time, HIGH or LOW
3
—
3
—
2
—
ns
xCEAB, xCEBA to xCLKAB, xCLKBA
tH
Hold Time HIGH or LOW
2
—
2
—
0
—
ns
xCEAB, xCEBA to xCLKAB, xCLKBA
tW
Pulse Width HIGH or LOW
3
—
3
—
3
—
ns
xCLKAB or xCLKBA(3)
tSK(o)
OutputSkew(4)
—
0.5
—
0.5
—
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Guaranteed but not tested
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT162952ETPV | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74FCT162H244CTPA | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:FCT SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| IDT74FCT162H244ETPA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT162H245ATPA | 制造商:Integrated Device Technology Inc 功能描述: |
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