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參數(shù)資料
| 型號： | IDT74FCT162952CTPA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 77K |
| 代理商： | IDT74FCT162952CTPA |
6
INDUSTRIALTEMPERATURERANGE
IDT74FCT162952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
Pulse
Generator
RT
D.U.T.
V CC
V IN
CL
V OUT
50pF
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCH RO NO US C O NTRO L
PRESET
C LEAR
ETC.
SYN CHRO N OU S C ON TR OL
tSU
tH
tREM
tSU
tH
PRESET
C LEAR
CLO CK ENABL E
ETC.
HIGH-LOW -HIG H
PULS E
LO W -H IG H-LOW
PULS E
tW
1.5V
SAME PHASE
INPUT TRAN SITIO N
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
O PPO SITE P HASE
INPUT TRAN SITIO N
3V
1.5V
0V
tPLH
tPHL
VOL
CON TRO L
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NO RMALLY
LO W
OUTPUT
NO RMALLY
HIGH
SW ITCH
CLO SE D
SW ITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
Set-up, Hold, and Release Times
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Pulse Width
TEST CIRCUITS AND WAVEFORMS
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相關(guān)代理商/技術(shù)參數(shù) |
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