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參數(shù)資料
| 型號： | IDT74FCT16500ETEG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | 0.635 MM PITCH, CERPACK-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 123K |
| 代理商： | IDT74FCT16500ETEG |
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IDT54/74FCT16500/AT/CT/ET
FASTCMOS18-BITREGISTEREDTRANSCEIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
AUGUST 1999
1999
Integrated Device Technology, Inc.
DSC-5433/-
c
IDT54/74FCT16500/AT/CT/ET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS 18-BIT
REGISTERED
TRANSCEIVER
DESCRIPTION:
The FCT16500AT/CT/ET 18-bit registered transceivers are built using
advanced dual metal CMOS technology. These high-speed, low-power
18-bit registered bus transceivers combine D-type latches and D-type flip-
flops to allow data flow in transparent, latched and clocked modes. Data flow
in each direction is controlled by output-enable (OEAB and
OEBA), latch
enable (LEAB and LEBA) and clock (
CLKAB and CLKBA) inputs. For A-
to-B data flow, the device operates in transparent mode when LEAB is high.
When LEAB is low, the A data is latched if
CLKAB is held at a high or low
logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the
high-to-low transition of
CLKAB. OEAB performs the output enable function
on the B port. Data flow from B port to A port is similar but uses
OEBA, LEBA
and
CLKBA. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
The FCT16500AT/CT/ET are ideally suited for driving high-capaci-
tance loads and low-impedance backplanes. The output buffers are
designed with power off disable capability to allow "live insertion" of boards
when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
B1
C
D
C
D
A1
LEAB
CLKAB
OEBA
LEBA
CLKBA
OEAB
TO 17 OTHER CHANNELS
C
D
C
D
1
30
28
27
55
2
3
54
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP
and 25 mil pitch CERPACK packages
Extended commercial range of -40°C to +85°C
VCC = 5V ±10%
High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit “l(fā)ive insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA =
25°C
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