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參數(shù)資料
| 型號(hào)： | IDT74FCT2646ATSO8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 198K |
| 代理商： | IDT74FCT2646ATSO8 |
INDUSTRIALTEMPERATURERANGE
IDT74FCT2646AT/CT
FASTCMOSOCTALTRANSCEIVER/REGISTER(3-STATE)
3
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
±1 A
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
±1 A
IOZH
High Impedance Output Current
VCC = Max
VO = 2.7V
—
±1 A
IOZL
(3-State output pins)(4)
VO = 0.5V
—
±1
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
—
±1 A
VIK
Clamp Diode Voltage
VCC = Min, IIN = -18mA
—
–0.7
–1.2
V
VH
Input Hysteresis
—
200
—
mV
ICC
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
0.01
1
A
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5A at TA = –55°C.
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
IODL
Output LOW Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
16
48
—
mA
IODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–16
–48
—
mA
VOH
Output HIGH Voltage
VCC = Min
IOH = –15mA
2.4
3.3
—
V
VIN = VIH or VIL
VOL
Output LOW Voltage
VCC = Min
IOL = 12mA
—
0.3
0.5
V
VIN = VIH or VIL
OUTPUT DRIVE CHARACTERISTICS
NOTES:
1. H = HIGH
L = LOW
X = Don't Care
↑ = LOW-to-HIGH transition.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored
on every LOW-to-HIGH transition on the clock inputs.
FUNCTION TABLE (1)
Inputs
Data I/O(2)
G
DIR
CPAB
CPBA
SAB
SBA
A1 - A8
B1 - B8
Operation
H
X
H or L
X
Input
Isolation
HX
↑↑
X
Store A and B Data
L
X
L
Output
Input
Real-Time B Data to A Bus
L
X
H or L
X
H
Stored B Data to A Bus
L
H
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Stored A Data to B Bus
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