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參數(shù)資料
| 型號： | IDT7M9521S250M |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 250 MHz, MICROPROCESSOR, XMA196 |
| 封裝： | MEZZANINE CONNECTOR-196 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 56K |
| 代理商： | IDT7M9521S250M |
5
1999
Integrated Device Technology, Inc.
DSC-4266/2
IDT
IDT7M9516/18/19/20/21/22/23
PIN DEFINITIONS (CONTINUED)
Signal Name
Signal Definition
Type
Description
ClkFreq(2:0)
SysCLK
Config
In normal mode these inputs specify the system bus clock frequency. In SmartClock
Frequency
Input
mode, these inputs specify the maximum system clock frequency.
000=45MHz (includes 43.75/44)
100=75MHz
001=50MHz
101=83MHz
010=60MHz (includes 58.33)
110=90MHz
011=66MHz
111=100MHz
INT*(5:0)
Interrupts
Input
General processor interrupts.
NMI*
Non-Maskable
Input
Non-maskableinterrupt
Interrupt
SoftRST*
SoftReset
Input
Asserting this input causes a processor soft (or warm) reset.
S_HardRST*
Synchronous
Input
Asserting this input causes a processor hard (or cold) reset.
Hard Reset
A_HardRST*
Asynchronous
Input
Asserting this input causes a processor hard (or cold) reset.
Hard Reset
RSTOut*
ResetOutput
Output
This pin is asserted by the C3 to reset system logic. This output is asserted during
power-on reset, and whenever HardRST* is asserted.
WDO*
WatchDog
Output
This pin asserted by the C3 whenever there is a timeout of the watchdog
Output
timer.
WD_Strb
WatchDog
Input
This pin must be strobed periodically by the system to prevent the Strobe watchdog timer
from timing out.
L2_HIT
L2 Cache Hit
Output
This pin indicates to the system that a hit has occurred in the on board
(ScMatch)
L2 cache. This pin is a no connect on the 7M9516/18/19/20/23.
ScDOE*
Secondary
Input
Only used when a secondary cache is implemented with the R5K internal
Cache Data
cache controller. This pin is a no connect on the 7M9516/18/19/20/23.
OE*
ScWord(1:0)
Secondary
I/O
Only used when a secondary cache is implemented with the R5K internal
Cache Word
cache controller
ScTCE*
Secondary Cache
Output
This pin indicates to the system when the L2 cache controller of the R5K is accessing the
Tag Chip Enable
Tag RAM. This pin is driven high by the 7M9516/18/19/20/23.
20MHz Out
20MHz Clock
Output
20MHz Clock
24MHz Out
24MHz Clock
Output
24MHz Clock
GND
Ground
Supply
System Ground
VCC3
+3.3V
Supply
System 3.3V Supply
VCC5
+5V
Supply
System 5V Supply
4266 tbl 03
ENVIRONMENTAL
Temp. (°C)
Humidity (1) Condition
Min
Max
Min
Max
Operating
0
55
20%
80%
Non-Op.
-10
60
10%
90%
Storage
-25
60
10%
90%
NOTE:
1. Non-Condensing
4266 tbl 02
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