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參數(shù)資料
| 型號(hào)： | IDTCSP59920-7SO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | IDTCSP59920-7SO |
4
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP59920
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
NOTES:
1. All timing tolerances apply for FNOM
≥25MHz. Guaranteed by design and characterization, not subject to production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outputs. See AC Test Loads.
4. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
5. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
6. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
7. Refer to Input Timing Requirements for more detail.
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
10
ns/V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
Reference Clock Input
25
85
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CSP59920-2
CSP59920-5
CSP59920-7
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FREF
REF Frequency Range
FS = LOW
25
—
35
25
—
35
25
—
35
MHz
FS = MID
35
—
60
35
—
60
35
—
60
FS = HIGH
60
—
85
60
—
85
60
—
85
tRPWH
REF Pulse Width HIGH (1, 7)
3—
—
3
—
3
—
ns
tRPWL
REF Pulse Width LOW (1, 7)
3—
—
3
—
3
—
ns
tSKEW
Zero Output Skew (All Outputs)(1, 3)
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
tDEV
Device-to-Device Skew( 1,2, 4)
—
0.75
—
1.25
—
1.65
ns
tPD
REF Input to FB Propagation Delay( 1,6)
0.25
00.25
0.5
00.5
0.7
00.7
ns
tODCV
Output Duty Cycle Variation from 50% (1)
1.2
01.2
1.2
01.2
1.5
01.5
ns
tORISE
Output Rise Time(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tOFALL
Output Fall Time(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(1)
—
0.5
—
0.5
—
0.5
ms
tJR
Cycle-to-Cycle Output Jitter
RMS
—
25
—
25
—
25
ps
Peak-to-Peak
—
200
—
200
—
200
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