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參數(shù)資料
| 型號(hào)： | IDTCSP59920-7SO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | IDTCSP59920-7SO |
5
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP59920
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
100
Output
VDD
C L
C L = 50pF (C L = 30p F for -2 and -5 devices)
t
OR IS E
t
OF AL L
0.8 V DD
0.2 V DD
≤ 3ns
80%
20%
0V
Vth = 0.5V DD
VDD
100
AC TEST LOADS AND WAVEFORMS
TEST LOAD
CMOS INPUT TEST WAVEFORM
CMOS OUTPUT WAVEFORM
REF
FB
Q
OTH ER Q
t
REF
t
PD
t
SKEW
t
SKEW
t
JR
t
ODCV
t
ODCV
t
RP W H
t
RP W L
AC TIMING DIAGRAM
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5)
and terminated with VDD/2.
tSKEW:
The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow,
etc.)
tODCV:
The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
相關(guān)PDF資料 |
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| IDTCSP59920-5SO | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
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參數(shù)描述 |
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| IDTCSPF2510C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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| IDTCSPF2510CPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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