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參數(shù)資料
| 型號： | IDTCSPT855PGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 855 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | IDTCSPT855PGI8 |
1
IDTCSPT855
2.5V PLL CLOCK DRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2005
Integrated Device Technology, Inc.
DSC-6203/11
c
IDTCSPT855
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
CLOCK DRIVER
PLL
CLK
6
7
23
22
FBIN
PWRDWN
24
9
AVDD
POWERDOWN
AND TEST
LOGIC
Y0
Y1
12
13
FBOUT
19
20
Y3
26
27
Y2
17
16
3
2
AUGUST 2005
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
PLL clock driver for DDR (Double Data Rate) synchronous
DRAM applications
Spread spectrum clock compatible
Operating frequency: 60MHz to 220MHz
Low jitter (cycle-to-cycle): ±50ps
Distributes one differential clock input to four differential clock
outputs
Enters low power mode and 3-state outputs when input CLK
signal is less than 20MHz or PWRDWN is low
Operates from a 2.5V supply
Consumes <200
μμμμμA quiescent current
External feedback pins (FBIN,
FBIN) are used to synchronize
outputs to input clocks
Available in TSSOP package
DESCRIPTION:
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer
that distributes one differential clock input pair(CLK,
CLK ) to four differential
output pairs (Y[0:3], Y [0:3]) and one differential pair of feedback clock outputs
(FBOUT,
FBOUT). WhenPWRDWNishigh,theoutputsswitchinphaseand
frequencywithCLK. When
PWRDWNislow,alloutputsaredisabledtoahigh-
impedance state (3-state), and the PLL is shut down (low-power mode). The
device also enters this low-power mode when the input frequency falls below
asuggesteddetectionfrequencythatisbelow20MHz(typical10MHz). Aninput
frequency detection circuit detects the low-frequency condition, and after
applying a >20MHz input signal, this detection circuit reactivates the PLL and
enables the outputs.
When AVDD is tied to GND, the PLL is turned off and bypassed for test
purposes. The CSPT855 is also able to track spread spectrum clocking for
reduced EMI.
Since the CSPT855 is based on PLL circuitry, it requires a stabilization time
to achieve phase-lock of the PLL. This stabilization time is required following
power up.
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
相關(guān)PDF資料 |
PDF描述 |
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| IDTCSPT855PGG | 855 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| IDTCSPT855P | 855 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| IDTQS3125S1G | 3125 SERIES, 4-BIT DRIVER, TRUE OUTPUT, PDSO14 |
| IDTQS316245PV8 | DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| IDTQS32390QG8 | OCTAL MULTIPLEXER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857ABV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857ABVI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857APA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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