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參數(shù)資料
| 型號(hào)： | IDTQS5917T-100TJ8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IDTQS5917T-100TJ8 |
INDUSTRIALTEMPERATURERANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
5
INPUT TIMING REQUIREMENTS
Symbol
Description
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
3
ns
FI
Input Clock Frequency, SYNC0, SYNC1 (1)
14
F2XQ
MHz
tPWC
Input clock pulse, HIGH or LOW
2
—
ns
DH
Duty cycle, SYNC0, SYNC1
25
75
%
NOTE:
1. The FI specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHING CHARACTERISTICS(1)
Symbol
Parameter
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 and Q/2 (1)
—
350
ps
tSKF
Output Skew Between Falling Edges, Q0-Q4 (1)
—
350
ps
tSKALL
Output Skew, All Outputs (1)
—
500
ps
tPW
Pulse Width, Q5, 2xQ outputs
TCY/2
0.65
TCY/2 + 0.65
ns
tPW
Pulse Width, Q0-Q4, Q/2outputs (1)
TCY/2
0.5
TCY/2 + 0.5
ns
tJ
Cycle-to-Cycle Jitter, 33MHz (3)
—
0.25
ns
tPD
SYNC Input to Feedback Delay, 28MHz
100
400
ps
tPD
SYNC Input to Feedback Delay, 33MHz, 50
Ω to 1.5V
100
400
ps
tLOCK
SYNC to Phase Lock
—
10
ms
tPZH
Output Enable Time, RST LOW to HIGH (2)
07
ns
tPZL
tPHZ
Output Disable Time, RST HIGH to LOW (2)
06
ns
tPLZ
tR,tF
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
NOTES:
1. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
2. Measured in open loop mode PLL_EN = 0.
3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information
on proper FREQ_SEL level for specified input frequencies.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTQS5917T100TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| IDTQS5917T-100TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| IDTQS5917T-100TQG | 功能描述:IC CLK DVR PLL 1:8 100MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDTQS5917T-100TQG8 | 功能描述:IC CLOCK GEN LVTTL 100MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDTQS5917T-132TJ8 | 功能描述:IC CLOCK GEN LVTTL 132MHZ 28PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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