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參數資料
| 型號： | IDTQS5917T-132TQ8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數： | 6/7頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IDTQS5917T-132TQ8 |
INDUSTRIALTEMPERATURERANGE
6
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2 is used for output enable/disable parameters.
TEST CIRCUIT 1 is used for all other timing parameters.
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5917T provides
for replication of incoming SYNC clock signals. Any manipulation of that
signal, such as frequency multiplying or inversion is performed by digital
logic following the PLL (see the block diagram). The key advantage of the
SIMPLIFIED DIAGRAM OF QS5917T FEEDBACK
Thephasedifferencebetweentheoutputandtheinputfrequenciesfeeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedback closed loop system. In most applications, the output will optimally
have zero phase shift with respect to the input. In fact, the internal loop filter
on the QS5917T typically provides within 150ps of phase shift between
input and output.
PLL circuit is to provide an effective zero propagation delay between the
output and input signals. In fact, adding delay circuits in the feedback path,
‘propagation delay’ can even be negative! A simplified schematic of the
QS5917T PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
TEST LOAD
300
Ω
30pF
7.0V
OUTPUT
300
Ω
20pF
VDD
OUTPUT
160
Ω
68
Ω
Q
Q/2
Q
VCO
/2
PHASE
DETECTOR
INPUT
2xQ
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDTQS5917T-132TQG | 功能描述:IC CLOCK GEN LVTTL 132MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDTQS5917T-132TQG8 | 功能描述:IC CLOCK GEN LVTTL 132MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDTQS5917T-70TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| IDTQS5917T-70TQG | 功能描述:IC CLOCK GEN LVTTL 70MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDTQS5917T-70TQG8 | 功能描述:IC CLOCK GEN LVTTL 70MHZ 28QSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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