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參數(shù)資料
| 型號： | IMISC612CYB |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO34 |
| 封裝： | SSOP-34 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 82K |
| 代理商： | IMISC612CYB |
SC612
Low Cost Clock Generator for VX with 1 SDRAM Bank
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
4/24/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 5
PRODUCT FEATURES
n
Supports Pentium and Cyrix CPU’s.
n
4 host (CPU) clocks
n
4 host (SDRM) clocks for additional SDRAM
support.
n
Optional common or mixed supply mode :
(VDD = B1VDD = B2VDD = 3.3V)
(VDD = 5V, B1VDD = B2VDD = 3.3V)
n
< 250 pS skew on CPU buffers
n
< 250 pS skew on PCI buffers
n
60 mA buffer switching current
n
F.A.S.T. (Frequency Augmentation System Test)
mode
n
34 Pin SSOP package for minimum board space
BLOCK DIAGRAM
REF
PLL1
PLL2
B
dly
XIN
XOUT
S2
S1
S0
B2VDD
B1VDD
REF1
CPU (1:4)
SDRM (1:4)
PCI (1:6)
48MHz
24MHz
4
6
F.A.S.T.#
REF2
FREQUENCY TABLE
S2
S1
S0
CPU
PCI
F.A.S.T.#
0
REF/2
REF/4
Tri-State
0
1
55
a.32
4.00%
0
1
0
75
a.32
5.00%
0
1
75
37.5
5.00%
1
0
50
25
4.35%
1
0
1
55
27.6
4.00%
1
0
60
30
5.00%
1
66.6
33.3
5.00%
a.32 = Asynchronous PCI.
CONNECTION DIAGRAM
APPLICATIONS
Pentium
or Cyrix CPU’s with any available chipset
support for PCI systems.
VDD
REF1
24 MHZ
48 MHZ
VSS
PCI1
PCI2
PCI3
VDD
PCI4
PCI5
PCI6
S2
REF2
VSS
F.A.S.T.#
VDD
XIN
XOUT
VSS
B2VDD
SDRM4
SDRM3
SDRM2
SDRM1
VSS
CPU4
CPU3
CPU2
CPU1
B1VDD
S0
S1
VSS
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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