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參數(shù)資料
| 型號： | IMISC680EYB |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 94K |
| 代理商： | IMISC680EYB |
SC680E
I
2C System Clock Buffer
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.7
2/17/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 8
Pin Description
PIN
No.
Pin
Name
PWR
I/O
TYPE
Description
11
REFIN
VDD
I
PAD
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 100.0 Mhz.
4,5
CLK(1:2)
VDD
O
BUF1
Low skew output clock
8,9
CLK(3:4)
VDD
O
BUF1
Low skew output clock
13, 14
CLK(5:6)
VDD
O
BUF1
Low skew output clock
17, 18
CLK(7:8)
VDD
O
BUF1
Low skew output clock
21, 28
CLK(9:10)
VDD
O
BUF1
Low skew output clock
31, 32
CLK(11:12)
VDD
O
BUF1
Low skew output clock
35, 36
CLK(13:14)
VDD
O
BUF1
Low skew output clock
40, 41
CLK(15:16)
VDD
O
BUF1
Low skew output clock
44, 45
CLK(17:18)
VDD
O
BUF1
Low skew output clock
38
OE
-
I
PAD
Buffer Output Enable pin. When driven to a logic low level this
pin is used to place all output clocks (CLK1:18} in a tri state
condition. This feature facilitates in production board level
testing to be easily implemented for the clocks that this device
produces. Has internal pull-up resistor.
24
SDATA
-
I/O
PAD
serial data of I
2C 2-wire control interface. Has internal pull-up
resistor.
25
SDCLK
-
I
PAD
Serial clock of I
2C 2-wire control interface. Has internal pull-up
resistor.
6, 10, 15,
19, 22,
30, 34,
39, 43
Vss
PWR
-
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
3, 7, 12,
16, 20,
33, 37,
42, 46
Vdd
-
PWR
-
Power for output clock buffers.
29, 23
Vdd
-
PWR
-
Power for core logic.
26, 27
Vss
-PWR
-
Ground supply pins for internal lcore logic pins.
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