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參數(shù)資料
| 型號： | IMISC680EYB |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 94K |
| 代理商： | IMISC680EYB |
SC680E
I
2C System Clock Buffer
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.7
2/17/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 3 of 8
2-Wire I
2C Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read
back. Sub-addressing is not supported, thus all preceeding bytes must be sent in order to change
one of the control bytes. The 2-wire control interface allows each clock output to be individually
enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is
stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA
while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on
SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as
complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is
a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the
acknowledge (low) signal on the SDATA wire following reception of each byte.
The device will not
respond to any other control interface conditions. Previously set control registers are retained.
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state
at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN#
pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be
acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below
desrcibed sequence (Byte 0, Byte 1, Byte 2, ....) will be valid and acknowledged.
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