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參數(shù)資料
| 型號(hào)： | IMISC693DXB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | IMISC693DXB |
SC693
Clock Generator for Pentium and 6X86 Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.4
4/23/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 5
PRODUCT FEATURES
n Integrates clock generator and distribution buffers
n Supports Pentium and Cyrix based designs
n < 250 ps typical buffer skew on PCLK and on BCLK
n Supports USB (Universal Serial Bus)
n Designed to Intel’s clock specification.
n 60 mA switching current
n 20
output impedance buffers
n Operates from 5V or 3.3V supply
n 28 Pin SOIC
n PCLK will operate at 5.0, 3.3, or 2.5V supply
FREQUENCY TABLE
S2
S1
S0
PCLK(MHz)
BCLK(MHz)
0
83.3
p.33.3
0
1
83.3
41.65
0
1
0
75
a.32
0
1
75
37.5
1
0
50
25
1
0
1
66.6
33.3
1
0
60
30
1
55
27.5
BLOCK DIAGRAM
PRODUCT DESCRIPTION
The IMISC693 provides the clock frequencies and
clock distribution buffers required on a Pentium
synchronous and asynchronous PCI system board. It
supports clocking requirements for Pentium, Pentium
Pro, and Cyrix CPU’s.
It is designed to the
specifications for supporting the 430HX and 440FX
chipsets. Available Pseudo-synchronous (p.33.3) and
asynchronous (a.32) PCI clocks (BCLK) allows this
device to be used with other chipsets (such as
SiS559X) at high host bus clock CPU’s while
maintaining the PCI bus clock within the 33.3 Mhz
specification. Fixed output clocks of 24MHz and
48MHz are frequency centered to meet the SIO and
USB specifications.
p.33.3 : Pseudo-synchronous 33.3 Mhz
a. 32 : Asynchronous 32 MHz
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
Xin
Xout
VSS
S2
PCLK1
PCLK2
VDDP
PCLK3
PCLK4
VSS
S1
S0
VDD
REF0
REF1
VDD
48 MHz
24 MHz
VSS
BCLK6
BCLK5
VDD
BCLK4
BCLK3
VSS
BCLK2
BCLK1
XI
XO
S0
S1
S2
OSC
PLL
1
PLL
2
B
2
REF(0:1)
PCLK (1:4)
BCLK (1:6)
48 MHZ
24 MHZ
VDD
VDDP
B
6
4
2
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