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參數(shù)資料
| 型號(hào)： | IN74HC651N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| 中文描述： | 八路三態(tài)總線收發(fā)器和D觸發(fā)器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 297K |
| 代理商： | IN74HC651N |
IN74HC652
6
FUNCTION TABLE
A
INPUTS
Dir.
OE CAB CBA SAB SBA
B
FUNCTION
INPUTS Both the A bus and the B bus are
inputs.
Z
The output functions of the A and B
bus are disabled.
INPUTS Both the A and B bus are used for
inputs to the internal flip-flops. Data at
the bus will be stored on low to high
transition of the clock inputs.
INPUTS The A bus are outputs and the B bus
are inputs.
L
H
at the A bus.
L
H
at the A bus. The data of the B bus
are stored to the internal flip-flops on
low to high transition of the clock
pulse.
X
The data stored to the internal flip-
flops, are displayed at the A bus.
H
L
the internal flip-flops on low to high
transition of the clock pulse. The
states of the internal flip-flops output
directly to the A bus.
OUTPUTS The A bus are inputs and the B bus
are outputs.
L
H
at the B bus.
L
H
at the A bus. The data of the B bus
are stored to the internal flip-flops on
low to high transition of the clock
pulse.
Qn
The data stored to the internal flip-
flops are displayed at the B bus.
L
H
the internal flip-flops on low to high
transition of the clock pulse. The
states of the internal flip-flops output
directly to the B bus.
OUTPUTS OUTPUTS Both the A bus and the B bus are
outputs
Qn
Qn
The data stored to the internal flip-
flops are displayed at the A and B bus
respectively.
Qn
Qn
The output at the A bus are displayed
at the B bus, the output at the B bus
are displayed at the A bus respec.
L
H
X
X
X
X
Z
X
X
INPUTS
OUTPUTS
X
*
X
X
L
L
H
L
H
The data at the B bus are displayed
L
L
X
*
X
L
The data at the B bus are displayed
X
*
X
X
H
Qn
X
*
X
H
H
L
The data at the B bus are stored to
INPUTS
X
X
*
L
X
L
H
L
H
The data at the A bus are displayed
H
H
X
*
L
X
The data at the B bus are displayed
X
X
*
H
X
X
X
*
H
X
L
H
The data at the A bus are stored to
H
L
X
X
H
H
H
H
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH
TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY
LOW TO TRANSITION OF THE CLOCK INPUTS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IN74HC652 | OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| IN74HC74 | Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS |
| IN74HC74AD | Replaced by SN74ABT541B : Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| IN74HC75A | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC75AD | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IN74HC652 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS |
| IN74HC652A | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Octal 3-State Bus Transceivers and D Flip-Flops High-Performance Silicon-Gate CMOS |
| IN74HC74 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS |
| IN74HC74A | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual D Flip-Flop with Set and Reset |
| IN74HC74AD | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual D Flip-Flop with Set and Reset |
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