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參數(shù)資料
| 型號： | IN74HC74 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS |
| 中文描述： | 雙D觸發(fā)器的設(shè)置和復(fù)位高性能硅柵CMOS |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 100K |
| 代理商： | IN74HC74 |
IN74HC74A
82
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C
to
-55
°
C
6.0
30
35
Symbol
Parameter
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Set or Reset to Q
or Q (Figures 2 and 4)
2.0
4.5
6.0
105
21
18
130
26
22
160
32
27
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25
°
C,V
CC
=5.0 V
39
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
≤
85
°
C
Symbol
Parameter
25
°
C to-55
°
C
80
16
14
≤
125
°
C
120
24
20
Unit
t
su
Minimum Setup Time, Data to Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
2.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
t
rec
Minimum Recovery Time, Set or
Reset Inactive to Clock (Figure 2)
2.0
4.5
6.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
ns
t
w
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IN74HC74AD | Replaced by SN74ABT541B : Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| IN74HC75A | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC75AD | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC75AN | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC86AD | Enhanced Product Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IN74HC74A | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual D Flip-Flop with Set and Reset |
| IN74HC74AD | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual D Flip-Flop with Set and Reset |
| IN74HC74AN | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS |
| IN74HC75A | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS |
| IN74HC75AD | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS |
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