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參數(shù)資料
| 型號： | IN74HC75A |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 雙路2位透明鎖存高性能硅柵CMOS |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 214K |
| 代理商： | IN74HC75A |
IN74HC75A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
25
°
C
to
-55
°
C
Symbol
Parameter
≤
85
°
C
≤
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, D to Q (Figures 1
and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLH
, t
PHL
Maximum Propagation Delay , D to Q
(Figures 1 and 5)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
PLH
, t
PHL
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Latch)
Typical @25
°
C,V
CC
=5.0 V
35
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
pF
TIMING REQUIREMENTS
(C
L
=50pF, Input t
r
=t
f
=6.0 ns)
V
CC
V
Guaranteed Limit
≤
85
°
C
Symbol
Parameter
25
°
C to
-55
°
C
≤
125
°
C
Unit
t
SU
Minimum Setup Time,
Input D to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time,Latch
Enable to D (Figure 4)
2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
ns
t
w
Minimum Pulse Width, Latch
Enable Input
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IN74HC75AD | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC75AN | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC86AD | Enhanced Product Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| IN74HC86AN | Quad 2-Input Exclusive OR Gate |
| IN74HC86 | Quad 2-Input Exclusive OR Gate High-Performance Silicon-Gate CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IN74HC75AD | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS |
| IN74HC75AN | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS |
| IN74HC86 | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate High-Performance Silicon-Gate CMOS |
| IN74HC86A | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad 2-Input Exclusive OR Gate |
| IN74HC86AD | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Quad 2-Input Exclusive OR Gate |
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