參數(shù)資料
型號: IN74HCT573AN
廠商: INTEGRAL JOINT STOCK COMPANY
英文描述: Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS
中文描述: 八路三態(tài)同相透明鎖存器高性能硅柵CMOS
文件頁數(shù): 4/5頁
文件大?。?/td> 115K
代理商: IN74HCT573AN
IN74HCT573A
411
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
25
°
C
to
-55
°
C
30
Symbol
Parameter
85
°
C
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
38
45
ns
t
PLH
, t
PHL
Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5)
30
38
45
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
t
PZH
, t
PZL
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
C
IN
C
OUT
Maximum Input Capacitance
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
15
15
15
pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
48
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
85
°
C
Symbol
Parameter
25
°
C to
-55
°
C
10
125
°
C
Unit
t
SU
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
13
15
ns
t
h
Minimum Hold Time, Latch
Enable to Input D
(Figure 4)
5
5
5
ns
t
w
Minimum Pulse Width, Latch
Enable (Figure 2)
15
19
22
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
500
500
500
ns
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參數(shù)描述
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