參數(shù)資料
型號(hào)： ISL6125EVAL1
廠商： Intersil Corporation
英文描述： Power Sequencing Controllers
中文描述： 電源順序控制器
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 488K
代理商： ISL6125EVAL1
3
FN9005.8
February 5, 2007
Pin Descriptions
PIN #
PIN NAME
FUNCTION
DESCRIPTION
23
VDD
Chip Bias
Bias IC from nominal 1.5V to 5V
10
GND
Bias Return
IC ground
1
ENABLE_1/
ENABLE#_1
Input to start on/off
sequencing.
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality
is disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE. ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE#.
Only ISL6128 has 2 ENABLE# inputs, 1 for
each 2 channel grouping. EN_1# for (A, B), and EN_2# for (C, D).
11
ENABLE#_2
24
RESET#
RESET# Output
RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for
stabilization of output voltages. RESET# will assert low upon UVLO not being satisfied or
ENABLE/ENABLE# being deasserted. The RESET outputs are open drain N channel FET and is
guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on
VDD and UVLO_X.
RESET#_2 only exists on ISL6128 for (C, D) group I/O.
9
RESET#_2
20
UVLO_A
Under Voltage Lock
Out/Monitoring
Input
These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference
and are filtered to ignore short (<30μs) transients below programmed UVLO level.
12
UVLO_B
17
UVLO_C
14
UVLO_D
21
DLY_ON_A
Gate On Delay
Timer Output
Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each
cap is charged with 1μA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current
source providing delay to the associated FETs GATE turn-on.
These pins are NC on ISL6126, ISL6127 and ISL6130.
8
DLY_ON_B
16
DLY_ON_C
15
DLY_ON_D
18
DLY_OFF_A
Gate Off Delay
Timer Output
Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a
capacitor to ground. Each cap is charged with a 1μA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down turning-off the FET.
These pins are NC on ISL6127.
13
DLY_OFF_B
3
DLY_OFF_C
4
DLY_OFF_D
2
GATE_A
FET Gate Drive
Output
ISL6125 Open
Drain Outputs
Drives the external FETs with a 1μA current source to soft start ramp into the load.
On the ISL6125 only, these are open drain outputs that can be pulled up to a maximum of
VDD voltage.
5
GATE_B
6
GATE_C
7
GATE_D
22
SYSRST#
System Reset I/O
As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low.
This input can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms
stabilization delay) from input signal on this pin being driven high to first GATE. As an output when
there is a UV condition, this pin pulls low. If common to other SYSRST# pins in a multiple IC
configuration, it will cause immediate and unconditional latch-off of all other GATEs on all other
ISL612X sequencers.
This pin is a NC on ISL6126 and ISL6128 and ISL6130.
19
No Connect
No Connect
No Connect
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
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