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參數(shù)資料
| 型號(hào)： | ISL6269A |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Performance Notebook PWM Controller(高性能筆記本PWM控制器) |
| 中文描述： | 高性能筆記本PWM控制器（高性能筆記本的PWM控制器） |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 313K |
| 代理商： | ISL6269A |
12
FN9253.2
May 30, 2007
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
V
IN
-V
OUT
-V
L
across it. The preferred low-side MOSFET
emphasizes low r
DS(ON)
when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
2
r
DS ON
)
_LS
For the high-side MOSFET, (HS), its conduction loss is
written as:
For the high-side MOSFET, its switching loss is written as:
Where:
- I
VALLEY
is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I
PEAK
is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t
ON
is the time required to drive the device into
saturation
- t
OFF
is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Q
BOOT
Where:
- Q
g
is the total gate charge required to turn on the
high-side MOSFET
-
Δ
V
BOOT
, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q
g
, of 25nC at V
GS
= 5V, and a
Δ
V
BOOT
of
200mV. The calculated bootstrap capacitance is 0.125μF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22μF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the compensation
components, and the FSET components. The island should be
connected to the rest of the ground plane layer at one point.
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R
FSET
and capacitor C
FSET
should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
(EQ. 16)
P
CON_LS
I
LOAD
1
D
–
(
)
≈
(EQ. 17)
P
CON_HS
I
LOAD
2
r
DS ON
(
)
_HS
D
=
(EQ. 18)
P
SW_HS
V
I
t
f
----------------------------------------------------------------
2
V
I
t
f
-------------------------------------------------------------
2
+
=
C
BOOT
-----------------------
=
(EQ. 19)
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
HIGH-SIDE
MOSFETS
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
ISL6269A
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| ISL6269ACRZ | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6269ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6269ACRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6269ACRZ-T WITH GOLD BOND WIRE ONLY, T&R - Tape and Reel |
| ISL6269AEVAL2 | 制造商:Intersil Corporation 功能描述:ISL6269A EVALUATION BOARD 2 - Bulk |
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