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| 型號： | ISL6271A |
| 廠商： | Intersil Corporation |
| 英文描述： | Integrated XScale Regulator |
| 中文描述： | 綜合Xscale的調(diào)節(jié) |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 588K |
| 代理商： | ISL6271A |
13
FN9171.1
Light Load Operation - DCM
A light load is defined when the output inductor ripple current
reaches zero before the next switching cycle. Under this
condition, the ISL6271A synchronous rectifier will turn off
emulating a diode to prevent negative inductor current. As
explained below, the switching frequency and losses
associated with turning on the synchronous rectifier will be
reduced to enhance the low current efficiency. The top
waveform in Figure 22 shows the phase voltage in DCM.
The middle waveforms include the error amplifier voltage,
ripple capacitor voltage and the boundaries of the hysteresis
comparator which track the EA output. The waveform at the
bottom is representative of the inductor current. Notice that
in a switching cycle the inductor current rises as the upper
P-MOSFET turns on, falls when the lower N-MOSFET turns
on, and stays at zero after the current reaches zero as a
result of diode emulation.
To understand the ISL6271A light load operation, look
carefully at the waveforms in the middle of Figure 22. Notice
that the voltage across the ripple capacitor, VRP, has a
minimum clamp voltage (typically 0.4V), and that the Error
Amplifier can go below this voltage (typically clamped to
0.2V). In DCM, the voltage across ripple capacitor will be
discharged each cycle to the clamp voltage. While the lower
hysteresis is below this voltage, the ripple capacitor will
remain clamped keeping the upper P-MOSFET off. As the
EA voltage increases so too will the lower threshold of the
hysteresis window until it reaches the ripple capacitor clamp
voltage (VCLMP). At this point, the upper FET will be
enabled and will turn on. The lighter the load, the lower the
error amplifier output is, and the longer the ripple capacitor
voltage stays at the VCLMP voltage. This results in a phase
node switching frequency that is proportional to load current
(that is, lower switching losses and higher efficiency at
lighter loads). In DCM the switching frequency will be lower
than in a heavy load, CCM.
A load transition from full load to no load will result in a finite
period of time during which the error amplifier settles to a
new steady state condition. As illustrated in Figure 23, the
SSR architecture inherent to the ISL6271A responds within
6μs of the mode change, slewing the error amplifier output
below the clamped ripple capacitor voltage and preventing
the upper FET from turning on. Prior to reaching the new
stability point, the phase node applies four phase pulses
before the controller forces the output voltage to the
prescribed regulation point. Once the output falls below the
reference voltage the controller then pumps up the output
voltage and enters its steady state DCM. Mode changes that
take the converter from CCM into DCM will have much
higher output voltage spike than a load step that remains in
CCM. Compared with competitive solutions the ISL6271A
responds very well during this severe mode change and it is
more than sufficient to meet Vcore tolerance specifications
as required by Intel.
Transition Between Light load and Heavy Load
Unlike most control topologies that require two sets of
circuits to control the light and heavy load operation, the
SRR control naturally switches between heavy and light load
with the same control circuit. As the load gets lighter, the
feedback forces the error amplifier output to a lower voltage
and when the lower threshold of the hysteresis window is
lower than VCLMP, light load operation begins. The scope
shot in Figure 24 illustrates a mode transition from a DCM
(10mA load current) to CCM (170mA) with trace 4 (GRN)
being the command pulse that initiates the mode change.
Prior to the load step, and while the converter is in DCM, the
ripple voltage is approximately 10mV and the ripple
frequency is 125kHz. In CCM, the converter operates at a
frequency of approximately 10X that of DCM and the ripple
is reduced by more than a factor of two.
FIGURE 22. SRR IN DCM
VRP
VCMP
VPH
ILO
CLAMPED VRP> LOWER HYS
CLAMPED VRP = > LOWER HYS
FIGURE 23. CCM TO DCM MODE
PHASE PULSES BEFORE LOOP IS CLOSED
LOOP CLOSES 6μs AFTER MODE CHANGE
DCM
CCM
ISL6271A
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| ISL6271ACR | 功能描述:IC REG PMIC 1BUCK 2LDO 20-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| ISL6271ACR-T | 功能描述:IC PMIC XSCALE PROCESSOR 20-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| ISL6271ACRZ | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6271ACRZ-T | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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