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參數資料
| 型號： | ISL6271ACRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Integrated XScale Regulator |
| 中文描述： | 0.8 A SWITCHING REGULATOR, PQCC20 |
| 封裝： | 4 X 4 MM, LEAD FREE, PLASTIC, MO-220-VGGD, QFN-20 |
| 文件頁數： | 15/16頁 |
| 文件大?。?/td> | 588K |
| 代理商： | ISL6271ACRZ-T |
15
FN9171.1
Internal ESD Structures
The ISL6271A input/output pins are protected from over-
voltage conditions by clamping the pin to one diode drop
above or below the VCC voltage rail. During shutdown it is
possible that the SDA and SCL pins have a voltage greater
than VCC. Under this condition, the ESD diodes will provide
a reverse current path to circuitry on VCC that can act as a
load on the back-up battery. To avoid this condition, interrupt
VCC from external circuitry if a voltage greater than VCC is
expected on any of the pins identified below.
Layout Recommendation
Since the ISL6271A can operate at a high switching
frequency, it is especially important to apply good layout
practices. Decoupling of the regulator’s input voltage
(PVCC) and minimizing the loop area associated with the
phase node output filter is essential for reliable operation.
Return currents from the load should find a low impedance
path to the PGND pin on the IC (Pin 8). Ideally, the core
voltage would be distributed to the embedded processor on
a low impedance power plane; however, a 30-50mil, short
trace should be sufficient. When implementing DVM it is
important to minimize inductance between the load and the
output filter. The processors can command slew rates of up
to 200mA/ns and local decoupling at the processor socket is
essential to satisfying this requirement.
References
[1] ISL6292 data sheet - Battery Charger
[2] EL7536 data sheet - System regulator
[3] C-Code examples for PWR_I2C bus communication -
Intersil support documentation available upon request.
[4] PHILLIPS I
2
C BUS Specification
[5] http://www.semiconductors.philips.com/buses/i2c/
[6] Technical Brief TB389 “
PCB Land Pattern Design and
Surface Mount Guidelines for MLF Packages”
FIGURE 26. INTERNAL ESD STRUCTURES
GND
PVCC
LVCC
VOUT
EN
SCL
SDA
VCC
FB
PGOOD
BFLT#
VPLL
VSRAM
SOFT
GND
BBAT
PGND
GND
OUTPUT CAP
VCC LPF
PVCC INPUT CAP
FB RES
OUTPUT
INDUCTOR
5x5x1mm
SOFT-START
CAP
LDO
OUTPUT
CAPS
SINGLE
PT. GND
FIGURE 27. COMPONENT PLACEMENT AND TOP COPPER
ISL6271A
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|---|---|
| ISL6271A | Integrated XScale Regulator |
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| ISL6271ACR-T | Integrated XScale Regulator |
| ISL6293 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
| ISL6293-2CR | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL6271AEVAL1 | 功能描述:EVALUATION BOARD FOR ISL6271A RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓撲結構:升壓 頻率 - 開關:3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6271CR | 制造商:Rochester Electronics LLC 功能描述:PLL & SRAM REGULATOR FOR INTEL PROCESSORS - Bulk 制造商:Intersil Corporation 功能描述: |
| ISL6271EVAL1 | 制造商:Intersil Corporation 功能描述:ISL6271, PLL & SRAM REGULATOR FOR INTEL PROCESSORS EVALUATIO - Bulk |
| ISL6273 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1.2A Low Quiescent Current 1.5MHz High Efficiency Synchronous Buck Regulator |
| ISL6273EVAL1 | 功能描述:EVAL BOARD 1 FOR ISL6273 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 線性穩(wěn)壓器 (LDO) 系列:* 產品變化通告:1Q2012 Discontinuation 30/Mar/2012 設計資源:NCP590MNDPTAGEVB Gerber Files 標準包裝:1 系列:- 每 IC 通道數:2 - 雙 輸出電壓:1.8V，2.8V 電流 - 輸出:300mA 輸入電壓:2.1 ~ 5.5 V 穩(wěn)壓器類型:正，固定式 工作溫度:-40°C ~ 85°C 板類型:完全填充 已供物品:板 已用 IC / 零件:NCP590MNDP 其它名稱:NCP590MNDPTAGEVB-NDNCP590MNDPTAGEVBOS |
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