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參數(shù)資料
| 型號： | ISL9N7030BLS3ST |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | 30V, 0.009 Ohm, 75A, N-Channel Logic Level UltraFET Trench Power MOSFETs |
| 中文描述： | 75 A, 30 V, 0.012 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 197K |
| 代理商： | ISL9N7030BLS3ST |
2002 Fairchild Semiconductor Corporation
ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application’s ambient temperature,
T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W) must be reviewed
to ensure that T
JM
is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 19
defines the R
θ
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are R
θ
JA
values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, P
DM
.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 19 or by calculation using Equation 2.
R
θ
JA
is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
(EQ. 1)
PDM
θ
JA
–
(
------------------------------
)
=
(EQ. 2)
R
θ
JA
26.51
Area
)
-------------------+
+
=
20
40
60
80
1
10
0.1
R
θ
JA
= 26.51+ 19.84/(0.262+Area)
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
)
FIGURE 19. THERMAL RESISTANCE vs MOUNTING PAD AREA
ISL9N7030BLP3, ISL9N7030BLS3ST
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