參數(shù)資料
型號(hào)： ISPGDX160A-5B272
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： In-System Programmable Generic Digital CrosspointTM
中文描述： DSP-CROSSBAR SWITCH, PBGA272
封裝： BGA-272
文件頁(yè)數(shù)： 13/25頁(yè)
文件大?。?/td> 326K
代理商： ISPGDX160A-5B272
13
Specifications
ispGDX Family
Download
.jed - JEDEC Device Programming File
Third-Party Timing Simulation
The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.
For In-System Programming, Lattice
’
s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice
’
s ISP Daisy
Chain Download software. This powerful Windows-
based tool can be launched from the Tool Bar or by
Invoking the Download option from the drop down menu
within the ispGDX Design System. ISP Daisy Chain
Download version 5.0 or above supports the ispGDX
Family devices.
Figure 5. ISP Device Programming Interface
ispGDX
80A
SDO
SDI
MODE
SCLK
ispEN
5-wire
Programming
Interface
ispGDX
120A
ispGDX
160/A
BSCAN/
ispEN
BSCAN/
ispEN
BSCAN/
ispEN
Figure 6. ispJTAG Device Programming Interface
ispGDX
80A
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
ispGDX
120A
ispGDX
160/A
BSCAN/
ispEN
BSCAN/
ispEN
BSCAN/
ispEN
VCC
In-System Programmability
All necessary programming of the ispGDX Family is done
via five TTL level logic interface signals. These five
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
On-chip programming can be accomplished using either
an IEEE 1149.1 boundary scan protocol or a Lattice
industry-standard ISP programming protocol. The IEEE
1149.1-compliant interface signals are Test Data In (TDI),
Test Data Out (TDO), Test Clock (TCK) and Test Mode
Select (TMS) control. The corresponding Lattice ISP
control signals are SDI, SDO, SCLK and MODE. These
signals switch their operation from IEEE 1149.1 bound-
ary scan protocol to Lattice ISP programming protocol
based on the state of the BSCAN/
ispEN
pin as shown in
Table 2. Figure 5 illustrates the block diagram for the ISP
programming interface. Figure 6 illustrates the block
diagram for the ispJTAG interface.
Table 2. Operating Mode Control Signals
Op Mode Signals/ispGDX
SDI, SDO, SCLK, MODE
0
Program Device Using Lattice ISP Protocol
TDI, TDO, TCK, TMS
1
Program Device or Normal Operation Using IEEE 1149.1 Protocol
BSCAN/ispEN
OPERATION
CONTROL PIN FUNCTION
相關(guān)PDF資料
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參數(shù)描述
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ISPGDX160A-7B272 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX160A-7Q208 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ispGDX160V-5B208 功能描述:模擬和數(shù)字交叉點(diǎn) IC USE ispGDX2 RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ispGDX160V-5B272 功能描述:模擬和數(shù)字交叉點(diǎn) IC USE ispGDX2 RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
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