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參數(shù)資料
| 型號： | ISPGDX160A-5B272 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | In-System Programmable Generic Digital CrosspointTM |
| 中文描述： | DSP-CROSSBAR SWITCH, PBGA272 |
| 封裝： | BGA-272 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大小： | 326K |
| 代理商： | ISPGDX160A-5B272 |
14
Specifications
ispGDX Family
Boundary Scan / ISP Programming and Test Options
The ispGDX devices provide IEEE1149.1a test capabil-
ity and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface. In addition,
ispGDX devices can be programmed via the Lattice ISP
programming interface using the same TAP serial inter-
face pins.
When the BSCAN/
ispEN
signal is high the ispGDX de-
vices enable Boundary Scan Test mode. Under this
mode the Boundary Scan data registers for the I/O pins
are organized in the order given below. Each
I/O register is structured as shown in Figure 7.
The operation of the boundary scan test circuitry in the
ispGDX160 is dependent on the fuse pattern programmed
into the device. The boundary scan circuitry on the
ispGDX160A, ispGDX120A and ispGDX80A operates
independently of the programmed pattern. This allows
customers using boundary scan test to have full test
capability with only a single BSDL file.
Table 3. I/O Shift Register Order
Figure 7. Boundary Scan I/O Register Cell
D
Q
M
U
X
D
Q
D
Q
D
Q
D
Q
M
U
X
M
U
X
M
U
X
M
U
X
Normal
Function
OE
I/O Pin
EXTEST
Update DR
SCANOUT (to next cell)
Clock DR
SCANIN
(from
previous
cell)
Shift DR
Normal
Function
OE
TOE
I/O Shift Reg Order/ispGDX
ispGDX80A
SDI/TDI, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9,
RESET
, Y1/TOE, Y0, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, SDO/TDO
ispGDX120A
SDI/TDI, I/O B15 .. B29, I/O C0 .. C29, I/O D0 .. D14, TOE, Y2, Y3,
RESET
, Y1, Y0, I/O B14 .. B0,
I/O A29.. A0, I/O D29 .. D15, SDO/TDO
ispGDX160/A
SDI/TDI, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, TOE, Y2, Y3,
RESET
, Y1, Y0, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, SDO/TDO
I/O SHIFT REGISTER ORDER
DEVICE
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