參數(shù)資料
型號(hào)： ISPGDX160VA-7B272I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： In-System Programmable 3.3V Generic Digital CrosspointTM
中文描述： EE PLD, 7 ns, PBGA272
封裝： BGA-272
文件頁(yè)數(shù)： 24/37頁(yè)
文件大?。?/td> 464K
代理商： ISPGDX160VA-7B272I
24
Specifications
ispGDX160V/VA
The ispGDX Design System Compiler
After the GDF file is created, the compiler checks the
syntax and provides helpful hints and the location of any
syntax errors. The compiler performs design rule checks,
such as, clock and enable designations, the use of input/
output/BIDI usage, and the proper use of attributes. I/O
connectivity is also checked to ensure polarity, MUX
selection controls, and connections are properly made.
Compilation is completed automatically and report and
programming files are saved.
Reports Generated
When the ispGDX system compiles a design and gener-
ates the specified netlists, the following output files are
created:
Report Files:
.log
.rpt
.mfr
.tsu
.tco
.tpt
Compiler History
Compiler Report
Maximum Frequency Timing Report
Set-up and Hold Timing Report
Clock to Out Timing Report
Timing Report
Simulation File:
.sim
Post-Route Simulation With LAC Format
Netlists:
.edo
.vlo
.ifo
.vho
.vhn
.vto
EDIF Output
Verilog Output
OrCAD Output
VHDL non-VITAL with Maximum Delays Output
VHDL non-VITAL with Maximum Delays Output
VHDL VITAL Output
Download:
.jed
JEDEC Device Programming File
Third-Party Timing Simulation
The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.
For In-System Programming, Lattice
’
s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice
’
s ISP Daisy
Chain Download software. This powerful Windows-based
tool can be launched from the Tool Bar or by Invoking the
Download option from the drop down menu within the
ispGDX Design System. ISP Daisy Chain Download
version 7.1 or above supports the ispGDX Family de-
vices.
ispGDX Development System (Continued)
相關(guān)PDF資料
PDF描述
ISPGDX160VA-7Q208 In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX160VA-7Q208I SMBPVA6 MOUNTING BRACKET KIT
ISPGDX160VA-9B208I In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX160VA-9B272I In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX160VA-9Q208I In-System Programmable 3.3V Generic Digital CrosspointTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPGDX160VA-7BN208 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX160VA-7BN208I 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX160VA-7Q208 功能描述:模擬和數(shù)字交叉點(diǎn) IC 3.3V 160 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX160VA-7Q208I 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX160VA-9B208I 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
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