參數(shù)資料
型號(hào)： ISPGDX240VA-9B388I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： In-System Programmable 3.3V Generic Digital CrosspointTM
中文描述： EE PLD, 9 ns, PBGA388
封裝： FBGA-388
文件頁(yè)數(shù)： 7/25頁(yè)
文件大?。?/td> 324K
代理商： ISPGDX240VA-9B388I
7
Specifications
ispGDX240VA
ADVANCED
4-to-1
16-Bit MUX
Bidirectional
Figure 6. Data Bus Byte Swapper
Figure 7. Four-Port Memory Interface
C
D
OEA OEB
I/OA
D0-7
D8-15
D8-15
D0-7
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
B
B
B
B
Port #1
OE1
Memory
Port
OEM
SEL0
SEL1
To
Memory
Port #2
OE2
Port #3
OE3
Note: All OE and SEL lines driven by external arbiter logic (not shown).
Port #4
OE4
Figure 5. Address Demultiplex/Data Buffering
C
M
Q
CLK
OEA
OEB
I/OA
I/OB
Address
Buffered
Data
To Memory/
Peripherals
XCVR
Address
Latch
Applications (Continued)
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-39 (240 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.
User Electronic Signature
The ispGDXVA Family includes dedicated User Elec-
tronic Signature (UES) E
2
CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Security
The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
相關(guān)PDF資料
PDF描述
ISPGDX80A-7T100 In-System Programmable Generic Digital CrosspointTM
ISPGDX120A-5Q160 In-System Programmable Generic Digital CrosspointTM
ISPGDX160A-5Q208 In-System Programmable Generic Digital CrosspointTM
ISPGDX160-5Q208 In-System Programmable Generic Digital CrosspointTM
ISPGDX80A-5T100 In-System Programmable Generic Digital CrosspointTM
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ISPGDX2-64/E 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:High Performance Interfacing and Switching
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ISPGDX80A-7T100 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX80VA-3T100 功能描述:模擬和數(shù)字交叉點(diǎn) IC 3.3V 80 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube
ISPGDX80VA3T100-5I 制造商:Lattice Semiconductor Corporation 功能描述:
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