- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384535 > ISPGDX80A-7T100 (LATTICE SEMICONDUCTOR CORP) In-System Programmable Generic Digital CrosspointTM PDF資料下載
參數(shù)資料
| 型號： | ISPGDX80A-7T100 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | In-System Programmable Generic Digital CrosspointTM |
| 中文描述： | DSP-CROSSBAR SWITCH, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 326K |
| 代理商： | ISPGDX80A-7T100 |
8
Specifications
ispGDX Family
External Timing Parameters
Over Recommended Operating Conditions
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
111
4.0
4.0
0.0
–
–
–
–
–
–
–
3.5
3.5
–
10.0
–
–
5.0
6.5
–
–
–
–
5
8.5
6.0
9.5
6.0
6.0
9.0
9.0
–
–
14.0
–
5.0
0.5
–
–
80.0
5.5
5.5
0.0
–
–
–
–
–
–
–
5.0
5.0
–
14.0
–
–
7.0
9.0
–
–
–
–
7.0
11.0
9.0
13.0
8.5
8.5
12.0
12.0
–
–
18.0
–
7.0
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
A
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
A
A
Data Propagation Delay from any I/O pin to any I/O pin
Data Propagation Delay from MUXsel Inputs to any Output
Clock Frequency with External Feedback
Input Latch or Register Setup Time before any Clk
Output Latch or Register MUX Data Setup Time before any Clk
Latch or Register Hold Time after any Clk
Output Latch or Register Clk (from Y
x
) to Output Delay
Input Latch or Register Clk (from Y
x
) to Output Delay
Output Latch or Register Clk (from I/O pin) to Output Delay
Input Latch or Register Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset pulse width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 across chip)
1. All timings measured with one output switching, fast output slew rate setting, except
t
sl
.
t
pd
t
sel
f
max(ext)
t
su1
t
su2
t
h
t
gco1
t
gco2
t
co1
t
co2
t
en
t
dis
t
toeen
t
toedis
t
wh
t
wl
t
rst
t
rw
t
sl
t
sk
DESCRIPTION
PARAMETER
TEST
1
COND.
#
( )
1
UNITS
-5
MIN. MAX.
-7
MIN. MAX.
2
8
0
10
4
20
30
40
50
60
70
I/O Cell Fanout
6
10
4
Maximum
GRP Delay vs. I/O Cell Fanout
ispGDX timings are specified with a GRP load (fanout) of
four I/O cells. The figure at right shows the Maximum
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK, MUXsel0-1). Global Clock signals, which do
not use the GRP, have no fanout delay adder.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPGDX120A-5Q160 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX160A-5Q208 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX160-5Q208 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX80A-5T100 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX120A-7Q160 | In-System Programmable Generic Digital CrosspointTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDX80VA-3T100 | 功能描述:模擬和數(shù)字交叉點 IC 3.3V 80 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX80VA3T100-5I | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPGDX80VA-3TN100 | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX80VA5T100 | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPGDX80VA-5T100 | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。