參數(shù)資料
型號(hào)： ISPGDXTMFAMILY
廠商： Lattice Semiconductor Corporation
元件分類： TVS-瞬態(tài)抑制二極管
英文描述： JT 100C 100#22D PIN RECP
中文描述： 在系統(tǒng)可編程通用數(shù)字CrosspointTM
文件頁(yè)數(shù)： 1/25頁(yè)
文件大小： 326K
代理商： ISPGDXTMFAMILY
ispGDX
TM
Family
In-System Programmable
Generic Digital Crosspoint
TM
ispgdx_08
1
Functional Block Diagram
Features
IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Three Device Options: 80 to 160 Programmable I/O
Pins
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
— PCI Compliant Output Drive
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
Slew Rate Control
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
ispGDX OFFERS THE FOLLOWING ADVANTAGES
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins B
Boundary
Scan
Control
I/O
Cells
ISP
Control
I
I
I/O Pins D
Description
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
Multi-Port Multiprocessor Interfaces
Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
相關(guān)PDF資料
PDF描述
ISPGDX160A-5B272 In-System Programmable Generic Digital CrosspointTM
ISPGDX80VA-7T100 In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX80VA-3T100 In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX80VA-5T100 In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX80VA-5T100I In-System Programmable 3.3V Generic Digital CrosspointTM
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