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參數(shù)資料
| 型號： | ISPGDXTMFAMILY |
| 廠商： | Lattice Semiconductor Corporation |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | JT 100C 100#22D PIN RECP |
| 中文描述： | 在系統(tǒng)可編程通用數(shù)字CrosspointTM |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 326K |
| 代理商： | ISPGDXTMFAMILY |
13
Specifications
ispGDX Family
Download
.jed - JEDEC Device Programming File
Third-Party Timing Simulation
The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.
For In-System Programming, Lattice
’
s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice
’
s ISP Daisy
Chain Download software. This powerful Windows-
based tool can be launched from the Tool Bar or by
Invoking the Download option from the drop down menu
within the ispGDX Design System. ISP Daisy Chain
Download version 5.0 or above supports the ispGDX
Family devices.
Figure 5. ISP Device Programming Interface
ispGDX
80A
SDO
SDI
MODE
SCLK
ispEN
5-wire
Programming
Interface
ispGDX
120A
ispGDX
160/A
BSCAN/
ispEN
BSCAN/
ispEN
BSCAN/
ispEN
Figure 6. ispJTAG Device Programming Interface
ispGDX
80A
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
ispGDX
120A
ispGDX
160/A
BSCAN/
ispEN
BSCAN/
ispEN
BSCAN/
ispEN
VCC
In-System Programmability
All necessary programming of the ispGDX Family is done
via five TTL level logic interface signals. These five
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
On-chip programming can be accomplished using either
an IEEE 1149.1 boundary scan protocol or a Lattice
industry-standard ISP programming protocol. The IEEE
1149.1-compliant interface signals are Test Data In (TDI),
Test Data Out (TDO), Test Clock (TCK) and Test Mode
Select (TMS) control. The corresponding Lattice ISP
control signals are SDI, SDO, SCLK and MODE. These
signals switch their operation from IEEE 1149.1 bound-
ary scan protocol to Lattice ISP programming protocol
based on the state of the BSCAN/
ispEN
pin as shown in
Table 2. Figure 5 illustrates the block diagram for the ISP
programming interface. Figure 6 illustrates the block
diagram for the ispJTAG interface.
Table 2. Operating Mode Control Signals
Op Mode Signals/ispGDX
SDI, SDO, SCLK, MODE
0
Program Device Using Lattice ISP Protocol
TDI, TDO, TCK, TMS
1
Program Device or Normal Operation Using IEEE 1149.1 Protocol
BSCAN/ispEN
OPERATION
CONTROL PIN FUNCTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPHEADER01 | 制造商:Xeltek Inc 功能描述:ISP10/D10 |
| ISPICR1 | 功能描述:ADAPTER IN-CIRCUIT PROGRAMMING RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
| ISPL1048E-100LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-100LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-100LT | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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