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參數(shù)資料
| 型號： | ISPGDXTMFAMILY |
| 廠商： | Lattice Semiconductor Corporation |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | JT 100C 100#22D PIN RECP |
| 中文描述： | 在系統(tǒng)可編程通用數(shù)字CrosspointTM |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 326K |
| 代理商： | ISPGDXTMFAMILY |
9
Specifications
ispGDX Family
-5
-7
PARAMETER #
2
Inputs
t
io
GRP
t
grp
MUX
t
muxd
t
muxs
Register
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
Data Path
t
rfdbk
t
iobp
t
ioob
t
muxc
(Yx Clk) 33 I/O Register Data Input MUX Delay
t
muxc
(I/O Clk) 34 I/O Register Data Input MUX Delay
t
iod
(Yx Clk)
35 I/O Register I/O Input MUX Delay
t
iod
(I/O Clk)
36 I/O Register I/O Input MUX Delay
Outputs
t
ob
37 Output Buffer Delay
t
obs
38 Output Buffer Delay, Slow Slew
t
oen
39 I/O Cell OE to Output Enabled
t
oedis
40 I/O Cell OE to Output Disabled
t
goe
41 Global Output Enable Delay
t
toe
42 Test OE Enable Delay
Clocks
t
cio
43 I/O Clock Delay
t
gy0/1/2/3
44 Clock Delay, Y0/1/2/3
Global Reset
t
gr
45 Global Reset to I/O Register/Latch
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
DESCRIPTION
1
MIN. MAX. MIN. MAX. UNITS
21 Input Buffer Delay
—
0.7
—
1.3
ns
22 GRP Delay
—
2.0
—
2.5
ns
23 I/O Cell MUX A/B/C/D Data Delay
24 I/O Cell MUX A/B/C/D Data Select
—
—
1.0
2.5
—
—
1.4
3.4
ns
ns
25 I/O Latch Delay
26 I/O Register Setup Time Before Clock
27 I/O Register Hold Time After Clock
28 I/O Register Clock to Output Delay
29 I/O Reset to Output Delay
—
—
—
—
—
1.6
1.6
2.4
1.6
0.7
—
—
—
—
—
2.2
1.8
3.6
2.2
1.0
ns
ns
ns
ns
ns
30 I/O Register Feedback Delay
31 I/O Register Bypass Delay
32 I/O Register Output Buffer Delay
—
—
—
—
—
—
—
0.2
0.4
0.1
1.1
2.1
4.1
5.1
—
—
—
—
—
—
—
0.3
0.6
0.7
1.2
3.2
5.1
7.1
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
0.9
5.9
0.8
0.8
2.5
8.2
—
—
—
—
—
—
1.3
8.3
1.1
1.1
3.6
10.9
ns
ns
ns
ns
ns
ns
—
—
0.7
2.4
—
—
1.0
2.8
ns
ns
—
12.3
—
15.0
ns
Internal Timing Parameters
1
Over Recommended Operating Conditions
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPHEADER01 | 制造商:Xeltek Inc 功能描述:ISP10/D10 |
| ISPICR1 | 功能描述:ADAPTER IN-CIRCUIT PROGRAMMING RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關產(chǎn)品:1-Wire? 設備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
| ISPL1048E-100LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-100LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-100LT | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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