參數(shù)資料
型號: ISPLSI1032-90LT
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: In-System Programmable High Density PLD
中文描述: EE PLD, 17 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 9/16頁
文件大?。?/td> 226K
代理商: ISPLSI1032-90LT
Specifications
ispLSI 1032
9
Maximum GRP Delay vs GLB Loads
ispLSI 1032-80
ispLSI 1032-60
ispLSI 1032-90
0126A-80-32-isp
1
2
3
4
8
12
16
GLB Loads
G
4
5
6
0
Power Consumption
ure 3 shows the relationship between power and operat-
ing speed.
Power consumption in the ispLSI 1032 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
50
100
150
200
250
0
10
20
30
40
50
60
70
f
max (MHz)
I
C
80
Notes: Configuration of eight 16-bit Counters
Typical Current at 5V, 25
C
ispLSI 1032
0127A-32-80-isp
ICC can be estimated for the ispLSI 1032 using the following equation:
ICC = 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
相關(guān)PDF資料
PDF描述
ISPLSI1032E-100LJ In-System Programmable High Density PLD
ISPLSI1032E-80LJ In-System Programmable High Density PLD
ISPLSI1032E-80LJ High-Density Programmable Logic
ISPLSI1032E-80LT In-System Programmable High Density PLD
ISPLSI1032E-80LT High-Density Programmable Logic
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