參數(shù)資料
型號(hào): ISPLSI2096E-180LT128
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: In-System Programmable SuperFAST⑩ High Density PLD
中文描述: EE PLD, 5 ns, PQFP128
封裝: TQFP-128
文件頁數(shù): 7/11頁
文件大?。?/td> 142K
代理商: ISPLSI2096E-180LT128
Specifications
ispLSI 2096E
7
ispLSI 2096E Timing Model
Note: Calculations are based upon timing specifications for the ispLSI 2096E-180L.
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
(0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)
3.6
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2-0042/2096E
3.4
7.9
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33 - 35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25 - 27
#43, 44
#36
Reset
Ded. In
#21
#29 - 32
GOE0, 1
#42
#40, 41
0491/2096E
Comb 4 PT Bypass #23
#45
#38,
#39
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