- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384542 > ISPLSI2128VL-135LT100I (LATTICE SEMICONDUCTOR CORP) 2.5V In-System Programmable SuperFAST⑩ High Density PLD PDF資料下載
參數(shù)資料
| 型號(hào)： | ISPLSI2128VL-135LT100I |
| 廠(chǎng)商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | EE PLD, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | ISPLSI2128VL-135LT100I |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
Specifications
ispLSI 2128VL
2
Functional Block Diagram
Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)
The 128-I/O 2128VL contains 128 I/O cells, while the 64-
I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control, and the output
drivers can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 3.3V signal levels to support
mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128VL device con-
tains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
Global
Routing
Pool
(GRP)
0139B/2128VL
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C7
C6
C5
C4
C3
C2
C1
C0
O
O
I
IN 5
IN 4
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Y
Y
Y
T
T
B4
B5
B6
B7
B0
B1
B2
B3
O
O
A0
A1
A2
A3
A4
A5
A6
A7
BSCAN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0
GOE 1
C
C
I
TDI/IN 0
TMS/IN 1
I
Generic Logic
Blocks (GLBs)
Global
Routing
Pool
(GRP)
0139B/2128VL.64IO
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C7
C6
C5
C4
C3
C2
C1
C0
O
I
IN 5*
IN 4*
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
I/O 47
I/O 46
I/O 45
I/O 44
Output Routing Pool (ORP)
Input Bus
C
Y
Y
Y
T
T
B4
B5
B6
B7
B0
B1
B2
B3
O
A0
A1
A2
A3
A4
A5
A6
A7
BSCAN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0
GOE 1
C
C
I
TDI/IN 0
TMS/IN 1
*Not available on 84-PLCC Device
I
Generic Logic
Blocks (GLBs)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2128VL-135LT176 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VL-135LT176I | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VL-150LB208 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VL-150LT100 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2128VL-150LT176 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2128VL-135LT176 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ispLSI2128VL-135LT176I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2128VL-150LB100 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ispLSI2128VL-150LB208 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI2128VL-150LQ160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。