參數(shù)資料
型號(hào)： IT8192F
英文描述： Analog LCD Monitor Controller|
中文描述： 模擬液晶顯示器控制器|
文件頁(yè)數(shù)： 43/93頁(yè)
文件大?。?/td> 942K
代理商： IT8192F
www.ite.com.tw 35
www.iteusa.com
System Configuration
6.4.19 Hsync/Vsync Period Difference Interrupt Control Register (HV_PD_INTR) —FF00:12 (FF12)
This register defines the Hsync/Vsync period difference interrupt control. When the current pixel counts for a
Hsync period or the current Hsync line counts for a Vsync period are different from the previous counts, it will
trigger the interrupt, if this register is enabled.
Bit
7
R/W
R/W
Default
0
Description
Hsync Line Counts Overflow Interrupt Control Register
(HS_INTR_EN)
1: Enabled.
0: Disabled.
Pixel Counts Overflow Interrupt Control Register (PIX_INTR_EN)
1: Enabled.
0: Disabled.
Vsync Total Interrupt Control (VDE_TOT_INTR)
1: Enabled.
0: Disabled.
Input Internal VDE Selection
1: By pass.
0: Generates from CFG_REG offset 1C.
No Connection Detection Interrupt Control Register (NCD1_INTR)
1: Enabled.
0: Disabled.
Hsync Period Difference Interrupt Control Register (HSYNC_INTR)
1: Disabled.
0: Enabled.
Vsync Period Difference Interrupt Control Register (VSYNC_INTR)
1: Disabled.
0: Enabled.
Wake Up Status Enable (WAKE_EN)
1: Enabled.
0: Disabled and clear the wake up status.
6
R/W
0
5
-
-
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
R/W
0
6.4.20 Hsync Line Count Difference Value Register (HL_DIFF) —FF00:13 (FF13)
This register defines the Hsync line count difference value. When the difference between the previous Hsync
line count in vertical total and the current count is greater than this register or overflow, it will generate the
interrupt to the MCU.
Bit
7-0
R/W
R/W
Default
0
Description
Hsync Line Count Difference Value (HL_DIFF)
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