參數(shù)資料
型號: IT8192F
英文描述: Analog LCD Monitor Controller|
中文描述: 模擬液晶顯示器控制器|
文件頁數(shù): 51/93頁
文件大?。?/td> 942K
代理商: IT8192F
www.ite.com.tw 43
www.iteusa.com
System Configuration
6.4.44 ADC Select 1 Register (ADC_SEL1) —FF00:2E (FF2E)
This register defines the input select_1 signal of ADC.
Bit
7:6
R/W
R/W
Default
0
Description
Select ADC Input Clock Source
00: ADC input clock from output clock of DLL sub-module.
01: ADC input clock from output clock of PLL_MONI sub-module.
1x: ADC input clock from external DPCLK pin.
RVTOPSEL_1
RVBOTSEL_1
GVTOPSEL_1
GVBOTSEL_1
BVTOPSEL_1
BVBOTSEL_1
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
-
0
0
0
6.4.45 ADC Select 0 Register (ADC_SEL0) —FF00:2F (FF2F)
This register defines the input select_0 signal of ADC.
Bit
7
6
5
4
3
2
1
0
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
0
0
0
0
0
0
0
Description
Reserved
EVREF
RVTOPSEL_0
RVBOTSEL_0
GVTOPSEL_0
GVBOTSEL_0
BVTOPSEL_0
BVBOTSEL_0
6.4.46 DLL Parameter (PHASE) High Byte Register (DLL_HPHASE) —FF00:30 (FF30)
This register defines some setting functions of DLL.
Bit
7
R/W
R/W
Default
0
Description
DLL Input Clock Source (DLL_EXT_CKIN_EN)
1: DLL input clock from external DPCLK pin.
0: DLL input clock from output clock of PLL_MONI sub-module.
DLL Clock Out Enable (DLL_TEST_OUT_EN)
1: Enable DLL output clock to DLL_TST pin.
0: Disabled.
DLL Test Mode Enable (DLL_TMODE_EN)
1: Enable DLL output clock /8 to GPIO14 pin.
0: Disabled.
Phase Parameter High Byte (DLL_PHASE[12:8])
6
R/W
0
5
R/W
0
4-0
R/W
00
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