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參數(shù)資料
| 型號： | IT8192F |
| 英文描述： | Analog LCD Monitor Controller| |
| 中文描述： | 模擬液晶顯示器控制器| |
| 文件頁數(shù)： | 61/93頁 |
| 文件大?。?/td> | 942K |
| 代理商： | IT8192F |
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LCD Controller (LCD)
8.3.6 Display Timing Strobe Tag Register (LBR_WPTR_L) —FF80:05 (FF85)
This register defines how many pixels have been written into the line buffers, so that the display timing will be
active to synchronize the capture and display timings.
Bit
7-0
R/W
R/W
Default
00
Description
Lower 8 bits of write pointer (LBR_WPTR[7:0])
8.3.7 Display Timing Strobe Tag Register (LBR_WPTR_H) —FF80:06 (FF86)
This register defines how many pixels have been written into the line buffers, so that the display timing will be
active to synchronize the capture and display timings. This register will be concatenated with LBR_WPTR_L
register to be a completed tag pointer.
Bit
7-4
R/W
R/W
Default
00
Description
Full and Empty Reference Tag (Empty_Full_Tag[3:0])
This register defines when the number of slots is empty, and when the
Line Buffer is in Full status. When the number of slots are filled, the Line
Buffers is in Empty status.
Reserved
3 MSB bits of Write Pointer (LBR_WPTR[10:8])
3
-
-
2-0
R/W
00
8.3.8 Display Timing Active Register (LBR_CRT_ACTIVE) —FF80:07 (FF87)
This register is used to turn on the display timing generation function. After the input resolution is detected and
the related registers are ported, this register should be turned on before the panel can be turned on to display
images.
Bit
7-4
3-1
R/W
-
R/W
Default
-
0
Description
Reserved
Total number of pixels for each scan line
High( LBR_HTOATL_H[10:8])
This register = real total pixels divides by two (High bytes)
PS: Low bytes are at FF80.
Display Timing Enable
1: Enabled.
0: Disabled.
0
R/W
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IT8201R | Over Clock Controller Specification IT8203R v0.1 (for Intel (5 VID)) | PC Product Line |
| IT8203R | Over Clock Controller Specification IT8206R v0.1 (for Intel (6 VID)) | PC Product Line |
| IT8206R | Over Clock Controller Specification IT8203R v0.1 (for Intel (5 VID)) | PC Product Line |
| IT8208M | PCI Arbiter Specification v0.3 | PC Product Line |
| IT8209R | PCI Arbiter|Reference Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT81B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|100V V(DRM)|8A I(T)RMS|TO-220 |
| IT81C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|100V V(DRM)|8A I(T)RMS|TO-220 |
| IT81F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|100V V(DRM)|8A I(T)RMS|TO-220 |
| IT81G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|100V V(DRM)|8A I(T)RMS|TO-220 |
| IT8201R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Over Clock Controller Specification IT8203R v0.1 (for Intel (5 VID)) | PC Product Line |
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