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參數(shù)資料
| 型號(hào)： | IT8206R |
| 英文描述： | Over Clock Controller Specification IT8203R v0.1 (for Intel (5 VID)) | PC Product Line |
| 中文描述： | 超過時(shí)鐘控制器規(guī)范IT8203R v0.1（英特爾（5 vid等））|個(gè)人電腦產(chǎn)品線 |
| 文件頁(yè)數(shù)： | 24/31頁(yè) |
| 文件大小： | 250K |
| 代理商： | IT8206R |
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6.1.15
www.ite.com.tw
IT8203R V0.1
18
IT8203R
GPIO A and B Synchronize Control Register (GPIOSYNR)— Offset 0x1A
Bit
7-2
1
R/W
RO
R/W
Default
0h
0h
Description
Reserved
GPIO 9-0 Data out trigger
If GPIO 9~0 synchronize enable (bit 0), if this bit set to 1, the GPIO9 ~0
data is output to PAD. Write 0 to reset this bit.
GPIO 9~0 Synchronize Enable
0: Disable GPIO 9-0 synchronize output.
1: Enable GPIO 9-0 synchronize output.
0
R/W
0h
6.1.16
Watch-Dog Timer Register (WDTR)— Offset 0x20
Bit
7-0
R/W
R/W
Default
0h
Description
Watch-Dog Timer
Read this register means how much time left that watch-dog will be
timeout.
6.1.17
Watch-Dog Timer Unit Register (WDTUR)— Offset 0x21
Bit
7-4
3-2
R/W
RO
R/W
Default
0h
0h
Description
Reserved
Watch-Dog Timer time-unit select
2’b00: 1 s
2’b01: 0.1 s
2’b10: 10 ms
2/b11: 1 ms
RSTOUT# pulse width select
2’b00: 1 s
2’b01: 0.1 s
2’b10: 10 ms
2/b11: 1 ms
1-0
R/W
0h
6.1.18
Watch-Dog Timer Control Register (WDTCSR)— Offset 0x22
Bit
7-2
1
R/W
RO
R/W
Default
0h
0h
Description
Reserved
Watch-Dog Time-out
0: No watch-dog timeout event
1: watch-dog timeout occurred. Writing 1 can clear this bit.
Watch-Dog Timer Enable
0: Disable watch-dog timer
1: Enable watch-dog timer
0
R/W
0h
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| IT8281M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Sequence Controller Specification IT8281M v0.1 (For Desktop Only) | PC Product Line |
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