參數(shù)資料
型號(hào)： IT8206R
英文描述： Over Clock Controller Specification IT8203R v0.1 (for Intel (5 VID)) | PC Product Line
中文描述： 超過時(shí)鐘控制器規(guī)范IT8203R v0.1（英特爾（5 vid等））|個(gè)人電腦產(chǎn)品線
文件頁數(shù)： 5/31頁
文件大?。?/td> 250K
代理商： IT8206R
www.ite.com.tw
IT8203R V0.1
i
Contents
CONTENTS
1.
Features .................................................................................................................................................1
2.
General Description..................................................................................................................................3
3.
Block Diagram..........................................................................................................................................5
4.
Pin Configuration......................................................................................................................................7
5.
IT8203 Pin Descriptions............................................................................................................................9
6.
Register Description ...............................................................................................................................11
6.1
Register Description.....................................................................................................................11
6.1.1
VID Output Control Register (VFOCR) — Offset 0x00 ......................................................12
6.1.2
VID Programmed Ouput Register (VIDPOR)— Offset 0x02 ..............................................12
6.1.3
VID Ouput Register (VIDOR)— Offset 0x03......................................................................12
6.1.4
VID Input Register (VIDIR)— Offset 0x04.........................................................................13
6.1.5
GPIOA Control Register (GPIOACR)— Offset 0x10..........................................................13
6.1.6
GPIO B Control Register (GPIOBCR)— Offset 0x11.........................................................13
6.1.7
GPIO A Data Register (GPIOADR)— Offset 0x12.............................................................14
6.1.8
GPIO B Data Register (GPIOBDR)— Offset 0x13.............................................................14
6.1.9
GPIO A Output Type Register (GPIOAOTR)— Offset 0x14 ..............................................15
6.1.10
GPIO B Output Type Register (GPIOBOTR)— Offset 0x15 ..............................................15
6.1.11
GPIO A Pull-up Resister Control Register (GPIOAPUR)— Offset 0x16.............................16
6.1.12
GPIO B Pull-up Resister Control Register (GPIOBPUR)— Offset 0x17.............................16
6.1.13
GPIO A Pull-down Resister Control Register (GPIOAPDR)— Offset 0x18 ........................17
6.1.14
GPIO B Pull-down Resister Control Register (GPIOBPDR)— Offset 0x19 ........................17
6.1.15
GPIO A and B Synchronize Control Register (GPIOSYNR)— Offset 0x1A........................18
6.1.16
Watch-Dog Timer Register (WDTR)— Offset 0x20...........................................................18
6.1.17
Watch-Dog Timer Unit Register (WDTUR)— Offset 0x21..................................................18
6.1.18
Watch-Dog Timer Control Register (WDTCSR)— Offset 0x22..........................................18
7.
DC Characteristics..................................................................................................................................19
8.
AC Characteristics..................................................................................................................................21
9.
Package Information...............................................................................................................................23
10.
Ordering Information...............................................................................................................................25
FIGURES
Figure 8-1. Serial Bus Waveform..................................................................................................................21
TABLES
Table 4-1. Pins Listed in Numeric Order.........................................................................................................8
Table 5-1. Pin Descriptions of VID Interface...................................................................................................9
Table 5-2. Pin Descriptions of General Purpose I/O........................................................................................9
Table 5-3. Pin Descriptions of SM Bus Interface.............................................................................................9
Table 5-4. Pin Description of Watch-Dog Reset..............................................................................................9
Table 5-5. Pin Description of CPU Changing Detection ..................................................................................9
Table 5-6. Pin Description of Power/Ground...................................................................................................9
Table 6-1. List of Over Clock Registers ........................................................................................................11
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