參數(shù)資料
型號: IT8208M
英文描述: PCI Arbiter Specification v0.3 | PC Product Line
中文描述: PCI仲裁器規(guī)格v0.3 |個人電腦產(chǎn)品線
文件頁數(shù): 18/31頁
文件大小: 250K
代理商: IT8208M
6.1.1
www.ite.com.tw
IT8203R V0.1
12
IT8203R
VID Output Control Register (VFOCR) — Offset 0x00
Bit
7-5
4
R/W
-
R/W
Default
0h
0h
Description
Reserved
Dynamic VID Enable bit
0: When this bit is set to “0”, the value of output pins VIDOUT[4:0] is the
same as the value of VIDPOR register.
1: When this bit is set to “1”, the value of VIDOUT output pins is generated
from the input signals VIDIN[4:0] and VIDPOR register.
This bit is active when bit 1 (VIDOE) is set to 1.
Clear New CPU Status (CLRCPU)
Write “1” to this bit to clear New CPU Status bit.
To release the clear action, this bit should be written to “0” after being
written to “1”.
This bit is always read as “0”.
Write “1” to clear this bit.
New CPU Status (NCPU)
0: CPU is not replaced.
1: CPU is replaced.
VID Output Enable (VIDOE)
0: VIDDIN4~VIDIN0 pins pass to VIDOUT4~VIDOUT0 pins.
1: VIDOUT4~VIDOUT0 pins are controlled by VIDPOR[4:0].
Reserved
3
WO
0h
2
RO
0h
1
R/W
0h
0
R/W
0h
6.1.2
VID Programmed Ouput Register (VIDPOR)— Offset 0x02
Bit
7-5
4-0
R/W
RO
R/W
Default
0h
0h
Description
Reserved
VID Programmed Output Data (VIDPOD[4:0])
The value is valid when VIDOE bit is “1”. The sum of VIDPOD and VIDIN is
output to VIDOUT4~VIDOUT0 output pins.
6.1.3
VID Ouput Register (VIDOR)— Offset 0x03
Bit
7-5
4-0
R/W
RO
RO
Default
0h
0h
Description
Reserved
VID Output Data (VIDOD[4:0])
These bits store the value of VIDOUT4~VIDOUT0
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相關代理商/技術參數(shù)
參數(shù)描述
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