參數(shù)資料
型號(hào)： IT8228E
英文描述： LPC Media I/F Specification v0.2 | PC Product Line
中文描述： LPC媒體我/女規(guī)格v0.2 |個(gè)人電腦產(chǎn)品線(xiàn)
文件頁(yè)數(shù)： 6/93頁(yè)
文件大?。?/td> 479K
代理商： IT8228E
www.ite.com.tw
IT8228E V0.2
ii
IT8228E
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
Smart Card Reader Base Address MSB Register (Index=60h, Default=03h)......................30
Smart Card Reader Base Address LSB Register (Index=61h, Default=38h).......................30
Smart Card Reader Interrupt Level Select (Index=70h, Default=09h)..................................30
Smart Card Reader Special Configuration Register 1 (Index=F0h, Default=02h)................30
Smart Card Reader Special Configuration Register 2 (Index=F1h, Default=7Fh)................31
7.9
GPIO Configuration Registers (LDN=05h)........................................................................................31
7.9.1
Interrupt Status Access Base Address MSB Register (Index=60h, Default=00h)................31
7.9.2
Interrupt Status Access Base Address LSB Register (Index=61h, Default=00h).................31
7.9.3
GPIO Pin Set 1, 2, 3, 4 and 5 Polarity Registers (Index=B0h, B1h, B2h, B3h and B4h,
Default=00h) .........................................................................................................................31
7.9.4
GPIO Pin Set 1, 2, 3, 4 and 5 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh,
BBh and BCh, Default=00h) .................................................................................................31
7.9.5
Simple I/O Set 1, 2, 3, 4 and 5 Output Enable Registers (Index=C8h, C9h, CAh, CBh and
CCh, Default=00h)................................................................................................................31
7.9.6
Simple I/O Set 1, 2, 3, 4, 5, and 6 Data Registers (Index=F0h, F1h, F2h, F3h, and F4h,
Default=00h) .........................................................................................................................32
7.9.7
SWC Status Register (SWC_STS) (Index=F5h, Default =--)...............................................32
7.9.8
SWC_STS to PME Enable Register (Index=F6h, Default=00h)...........................................33
7.9.9
SWC_STS to SMI Enable Register (Index=F7h, Default=00h) ............................................34
8.
Functional Description..................................................................................................................................35
8.1
LPC Interface.....................................................................................................................................35
8.1.1
LPC Transactions .................................................................................................................35
8.1.2
LDRQ# Encoding..................................................................................................................35
8.2
Serialized IRQ....................................................................................................................................35
8.2.1
Continuous Mode..................................................................................................................35
8.2.2
Quiet Mode ...........................................................................................................................35
8.2.3
Waveform Samples of SERIRQ Sequence..........................................................................36
8.2.4
SERIRQ Sampling Slot.........................................................................................................37
8.3
General Purpose I/O..........................................................................................................................38
8.4
Power Management Event (PME#)...................................................................................................39
8.5
SD Host Controller (SDC)..................................................................................................................39
8.5.1
Overview...............................................................................................................................39
8.5.2
Features................................................................................................................................39
8.5.3
Register Descriptions............................................................................................................39
8.5.3.1
SD Command Register (SD_CMD) .........................................................................41
8.5.3.2
SD Command Mode Register (SD_CMD_MD)........................................................42
8.5.3.3
SD Port Selection Register (SD_PORTSEL)...........................................................43
8.5.3.4
SD Command Argument Register (SD_ARG4, SD_ARG3, SD_ARG2, and
SD_ARG1)...............................................................................................................................43
8.5.3.5
Data Stop Register (SD_STOP)...............................................................................43
8.5.3.6
Transfer Sector Counter Enable Register (SD_SEC_EN).......................................44
8.5.3.7
Transfer Sector Count Register (SD_SECCNTL and SD_SECCNTH) ...................44
8.5.3.8
SD Memory Card Response Register (SD_RSP0 – SD_RSP14)............................44
8.5.3.9
SD Memory Card Information Register (SD_INFOL and SD_INFOH).....................46
8.5.3.10
SD Memory Card Buffer Status Register (SD_BUFSTS) ........................................47
8.5.3.11
SD Memory Card Error Register (SD_ERR)............................................................47
8.5.3.12
SD
Memory
Card
Information
SD_INFOH_MASK).................................................................................................................49
8.5.3.13
SD Memory Card Buffer Status Mask Register (SD_BUFSTS_MASK)...................49
8.5.3.14
SD Memory Card Error Mask Register (SD_ERR_MASK)......................................50
8.5.3.15
SD Clock Enable Register (SD_CLKEN).................................................................50
8.5.3.16
SD Clock Devisor Register (SD_CLK_DIV).............................................................51
Mask
Register
(SD_INFOL_MASK
and
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IT8281M 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Power Sequence Controller Specification　 IT8281M v0.1 (For Desktop Only) | PC Product Line
IT8282M 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Power Sequence Controller Specification　 IT8281M v0.1 (For Desktop Only) | PC Product Line
IT82B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220
IT82C 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220
IT82F 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220
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