參數(shù)資料
型號: IT8228E
英文描述: LPC Media I/F Specification v0.2 | PC Product Line
中文描述: LPC媒體我/女規(guī)格v0.2 |個人電腦產(chǎn)品線
文件頁數(shù): 61/93頁
文件大?。?/td> 479K
代理商: IT8228E
8.5.3.16 SD Clock Devisor Register (SD_CLK_DIV)
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IT8228E V0.2
51
Functional Description
The SD Clock Enable, a
read/write
register, enables the SDCLK divisor.
Index: 25h
Bit
R/W
Default
7 – 0
R/W
20h
SD Clock Divisor Select (SD_CLK_DIV)
Frequency of SDCLK is the frequency of the clock source of SD I/F
Controller (48MHz or 33MHz, selected by bit 1 of Clock Selection register.
Please refer to 8.3.6) divided by Divisor.
00h: Divisor = 2
01h: Divisor = 4
02h: Divisor = 8
04h: Divisor = 16
08h: Divisor = 32
10h: Divisor = 64
20h: Divisor = 128
40h: Divisor = 256
80h: Divisor = 512
Else: Reserved
8.5.3.17 SD Transfer Data Length Register (SD_SIZEL and SD_SIZEH)
Description
The SD Transfer Data Length, a 10-bit
read/write
register, determines the transfer data length. For SD
memory multiple Read, software can only set 512 Bytes. If an undefined code is selected, the transfer data
length will be 512 Bytes.
Index: 26h (SD_SIZEL)
Bit
R/W
Default
7 – 3
R/W
00h
Transfer Data Length [7:0] (LEN [7:0])
Index: 27h (SD_SIZEH)
Bit
R/W
Default
7 – 2
--
--
Reserved for ITE use.
1 – 0
R/W
2h
Transfer Data Length [9:8] (LEN [9:8])
Description
Description
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