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參數(shù)資料
| 型號： | IT8228E |
| 英文描述： | LPC Media I/F Specification v0.2 | PC Product Line |
| 中文描述： | LPC媒體我/女規(guī)格v0.2 |個人電腦產(chǎn)品線 |
| 文件頁數(shù)： | 79/93頁 |
| 文件大小： | 479K |
| 代理商： | IT8228E |
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8.7.3.8
The MS Interrupt Control, an 8-bit
read/write
register, is used to enable some interrupt events for the MS
controller.
Address: Base address + 6h
Bit
R/W
Default
7
R/W
0b
Interrupt Enable (INTEN)
Interrupt is enabled when “1” and disabled when “0”. An interrupt is
generated when an interrupt condition occurs after INTEN has been set to
“1”.
6
R/W
0b
Data Request Interrupt Enable (DRQSL)
Interrupt during data transfer request is enabled when “1” and disabled when
“0”. An interrupt is generated when an interrupt condition occurs after INTEN
has been set to “1”.
5
R/W
0b
Card Detect Interrupt Enable (CDIEN)
Interrupt for MSDET (MSDET_S) level changing is enabled when “1” and
disabled when “0”.
4
R/W
0b
Power On (PWRON)
MSPWR (MSPWR_S) is low when “1” and High-Z when “0”.
3 – 2
-
-
Reserved for ITE use.
[cont’d]
Bit
R/W
Default
1
R/W
0h
Auto Command (ACD)
When this bit is set to “1”, an ACD command is automatically executed after
an INT is detected. When “0”, disable the ACD command.
0
R/W
0h
Rise Edge Data (RED)
When this bit is set to “1”, serial data are loaded at the falling edge of the
clock. When “0”, loaded at the rising edge.
www.ite.com.tw
IT8228E V0.2
69
Functional Description
MS Interrupt Control Register
Description
Description
相關PDF資料 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IT8281M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Sequence Controller Specification IT8281M v0.1 (For Desktop Only) | PC Product Line |
| IT8282M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Sequence Controller Specification IT8281M v0.1 (For Desktop Only) | PC Product Line |
| IT82B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220 |
| IT82C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220 |
| IT82F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|200V V(DRM)|8A I(T)RMS|TO-220 |
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