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參數(shù)資料
| 型號(hào)： | IT8282M |
| 英文描述： | Power Sequence Controller Specification IT8281M v0.1 (For Desktop Only) | PC Product Line |
| 中文描述： | 電源順序控制器規(guī)格IT8281M v0.1（臺(tái)式機(jī)專用）|個(gè)人電腦產(chǎn)品線 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 92K |
| 代理商： | IT8282M |
7. AC Characteristics
www.ite.com.tw
IT8281M V0.1
13
AC Characteristics
Table 7-1. AC Timing Parameter
Item
t0
t1
t2
Max
50us +
t_vdimm_gd
Typ
1us
50us
Min
0
50us
Description
The falling edge of SB_PSON# to the assertion of ATX_PSON#.
The rising edge of ATX_PWRGD to the assertion of VDIMM_STR_EN
The assertion of VDIMM_STR_EN to the assertion of VDDA_EN.
The t_vdimm_gd is the rise time of the VDIMM_STR_EN voltage from
0V to 2.25V.
The assertion of VDDA_EN to the assertion of VCORE_EN.
The t_vdda_gd is the rise time of the VDDA voltage from 0V to 2.25V.
The rising edge of VCORE_GD to the assertion of VLDT_EN.
The assertion of VLDT_EN to the assertion of CPU_PWRGD and
SB_PWRGD.
The t_vldt_gd is the rise time of the vldt voltage from 0V to 1.0V.
The de-assertion of CPU_PWRGD and SB_PWRGD to the
de-assertion of VLDT_EN.
The de-assertion of VLDT_EN to the de-assertion of VCORE_EN.
The falling edge of VCORE_GD to the de-assertion of VDDA_EN.
The de-assertion of VDDA_EN to the de-assertion of VDIMM_STR_EN
or ATX_PSON#.
The de-assertion of VDIMM_STR_EN to the de-assertion of
ATX_PSON#.
The rising edge of SB_PSON# to the de-assertion of CPU_PWRGD
and SB_PWRGD.
t3
50us +
t_vdda_gd
50us +
t_vldt_gd
50us
t4
t5
50us
50us
t6
50us
t7
t8
t9
10ms
10ms
10ms
t10
50ms
t11
50us
Power on
Enter S3
Exit S3
Power off
t0
t1 t2 t3
t4 t5
t11 t6 t7
t8 t9
t0
t1 t3
t4 t5
t11 t6 t7
t8 t9 t10
ACPI_S3
SB_PSON#
ATX_PSON#
ATX_PWRGD
VDIMM_STR_EN
VDDA_EN
VCORE_EN
VCORE_GD
VLDT_EN
CPU_PWRGD
SB_PWRGD
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