參數(shù)資料
型號(hào)： IT8712F
英文描述： EC-LPC I/O Programming Guide EC-v0.2 | PC Product Line
中文描述： 歐盟預(yù)測(cè)編碼的I / O編程指南歐共體v0.2 |個(gè)人電腦產(chǎn)品線
文件頁數(shù)： 18/30頁
文件大小： 311K
代理商： IT8712F
4.5
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IT8710F Programming Guide
Parallel Port (LDN=03h)
Table 4-4. Parallel Port Configuration Registers
Default
00h
Parallel Port Activate
03h
Parallel Port Primary Base Address MSB Register
78h
Parallel Port Primary Base Address LSB Register
07h
Parallel Port Secondary Base Address MSB Register
78h
Parallel Port Secondary Base Address LSB Register
00h
POST Data Port Base Address MSB Register
80h
POST Data Port Base Address LSB Register
07h
Parallel Port Interrupt Level Select
03h
Parallel Port DMA Channel Select
Note1
03h
Note2
Parallel Port Special Configuration Register
LDN
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
Note 1:
When the ECP mode is not enabled, this register is
read only
as “04h”, and cannot be written.
Note 2:
When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP
mode cannot be enabled. Bit 0 of this register is always 0.
4.5.1
SPP and EPP Modes
Index
30h
60h
61h
62h
63h
64h
65h
70h
74h
F0h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration Register or Action
Table 4-5. Address Map and Bit Map for SPP and EPP Modes
Address
R/W
D0
D1
Base 1+0h R/W
PD0
PD1
Base 1+1h RO
TMOUT
1
Base 1+2h R/W
STB
AFD
Base 1+3h R/W
PD0
PD1
Register
Data Port
Status Port
Control Port
EPP Address
Port
EPP Data Port0 Base 1+4h R/W
EPP Data Port1 Base 1+5h R/W
EPP Data Port2 Base 1+6h R/W
EPP Data Port3 Base 1+7h R/W
D2
PD2
1
INIT SLIN IRQE
PDDIR
PD2
PD3
D3
PD3
ERR# SLCT
D4
PD4
D5
PD5
PE
D6
PD6
ACK# BUSY# SPP/EPP
1
1
PD6
PD7
D7
PD7 SPP/EPP
Mode
SPP/EPP
EPP
PD4
PD5
PD0
PD0
PD0
PD0
PD1
PD1
PD1
PD1
PD2
PD2
PD2
PD2
PD3
PD3
PD3
PD3
PD4
PD4
PD4
PD4
PD5
PD5
PD5
PD5
PD6
PD6
PD6
PD6
PD7
PD7
PD7
PD7
EPP
EPP
EPP
EPP
Note 1:
The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60,
0X61).
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