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參數(shù)資料
| 型號： | IT8712F |
| 英文描述： | EC-LPC I/O Programming Guide EC-v0.2 | PC Product Line |
| 中文描述： | 歐盟預測編碼的I / O編程指南歐共體v0.2 |個人電腦產(chǎn)品線 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 311K |
| 代理商： | IT8712F |
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Programming Sequence and Flow Charts
MIDI (LDN=0Ah)
Table 4-12.
MIDI Port Configuration Registers
Default
00h
MIDI Port Activate
03h
MIDI Port Base Address MSB Register
00h
MIDI Port Base Address LSB Register
0Ah
MIDI Port Interrupt Level Select
00h
MIDI Port Special Configuration Register
LDN
0Ah
0Ah
0Ah
0Ah
0Ah
Index
30h
60h
61h
70h
F0h
R/W
R/W
R/W
R/W
R/W
R/W
Configuration Register or Action
The IT8710F supports the MIDI capability by incorporating hardware to emulate the MPU-401 in the UART
mode. It is software compatible with MPU-401 interface, but only supports the
UART mode
(non-intelligent
mode). The UART is used to convert parallel data to the serial data required by MIDI. The serial data format is
RS-232 like: 1 start bit, 8 data bits, and 1 stop bit. The serial data rate is fixed at 31.25 Kbaud.
The MPU-401 logical device occupies two consecutive I/O spaces. The device also uses an interrupt. Both the
base address and the interrupt level are programmable. MIDI Base+0 is the MIDI Data port, and MIDI Base+ 1
is the Command/Status port.
MIDI Data Port:
The MIDI Data Port is used to transmit and receive MIDI data. When in UART mode, all transmit data is
transferred through a 16-byte FIFO and receive data through another 16-byte FIFO.
UART Mode:
1.
All reads of the Data port, MIDI Base+0, return the next byte in the receive buffer FIFO. The serial data
received from the MIDI_IN pin is stored in the receive buffer FIFO. The bit 7 RXS of the Status register is
updated to reflect the new receive buffer FIFO status. The receive data available interrupt will be issued
only if the FIFO has reached its programmed trigger level. The interrupts will be cleared as soon as the
FIFO drops below its trigger level. The trigger level is programmable by changing bits 2-1 of the MIDI port
Special Configuration Register, LDN8_F0h.
2.
All writes to the Data port, MIDI Base+0, are placed in the transmit buffer FIFO. Whenever the transmit
buffer FIFO is not empty, the data bytes are read from the buffer in turn and sent out from the MIDI_OUT
pin. The bit 6 TXS of the Status Register is updated to reflect the new transmit buffer FIFO status.
3.
All writes to the Command port, MIDI Base+1, are monitored and acknowledged below:
FFh:
Set the interface into the initialization condition. The interface returns to the intelligent mode
Others:
No operation
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