參數(shù)資料
型號(hào)： IXE5418
元件分類： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 14/30頁(yè)
文件大小： 367K
代理商： IXE5418
Intel Media Switch
IXE5418 Gigabit Device
14
Data Sheet
section, and the packet occupies the next 3 sections, for a total of 128 bytes. The next packet header
will then occupy the next 32 byte section in CPU memory. The CPU should decrement the Level
Counter by the 4 for the above example.
There is a per queue bit that allows the CPU to turn off any queue from writing packets into the
CPU memory.The IXE5418 prepends a 32-byte header to every packet sent to the CPU.
The IXE5418 expects the CPU to prepend a 32-byte header to every packet it receives from the
CPU. This header allows the CPU to inform the IXE5418 on a packet by packet basis whether the
IXE5418 should do an address resolution on the source and destination addresses, or whether it
should use the information in the header to switch the packet.
5.11
Unresolved Packet Transfers to CPU
The IXE5418 also maintains four queues for unresolved packets.
Each queue can be individually turned on or off and assigned a guaranteed bandwidth. This allows
the CPU to prioritize the types of packets that it wants to process.
The DMA engines provided per queue allow the IXE5418 to directly transfer data into the CPU
memory without CPU intervention.
The only difference between “unresolved packet transfers to CPU” versus “resolved packet
transfers to CPU”, is that unresolved packets have an option to not send the whole packet, but only
part of the packet to the CPU. The value by which the read pointer should be incremented, and the
value that should be written to the Level Counter register can be determined from the Unres Xfer
Size field of the header.
For example, if the Unres Xfer Size field contains 0, then the Read Pointer should be incremented
by 32 + 32 = 64 bytes, and the Level Counter register should be written with a value of 64
.
5.11.1
Unresolved Queues
Unresolved Queue entries use the following values:
Queue 3
— Layer 2 packets with source unresolved.
— Layer 2 packet with source port moved.
— Layer 2 packets include ARP and RARP packets. If IP and IPX switching and routing are
disabled, all packets are treated as Layer 2 packets.
Queue 2—If IP/IPX switching and routing is enabled:
— IPX and IP packets unresolved source.
— IPX and IP packets with source port move.
Queue 1—packets include:
— IP and IPX packets that need to be routed, but for which the destination swap valid bit not
set.
— Layer 4 packets with source or destination unresolved, given that the other is resolved.
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