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參數(shù)資料
| 型號： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 1/100頁 |
| 文件大?。?/td> | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet
Controller
Datasheet
Product Features
The IXF440 Multiport 10/100 Mbps Ethernet Controller (also called the
IXF440) provides eight 10/100 Mbps intelligent, high-performance MAC ports.
It includes network management support and is optimized for switch
applications.
I
Integration
—Eight Ethernet 10/100 Mbps MAC ports
—Onchip scrambler, descrambler, and PCS
functions for 100BASE-X connection
—Handles SNMP and RMON counters
I
IX Bus
—Supports a 4 Gbps high bus bandwidth
—Variable bus speed of 25 to 66 MHz
operational, and from 16 MHz for testing
—Interfaces a 64-bit bus with a 32-bit optional
mode
—Supports concurrent unidirectional 32-bit
buses for transmit and receive in split IX Bus
mode
—Provides transmit- and receive-independent
256-byte FIFOs for each of the eight ports
—Offers a generic slave FIFO interface
—Supports little or big endian byte ordering
—Supports transmit and receive byte alignment
—Supports receive packet fragmentation on byte
boundaries (replay feature)
—Provides programmable transmit and receive
bus thresholds
—Appends packet status to received packet
I
Performance
—Allows status register access without
interrupting packet transfer
—Enables early address filtering ability, with
packet header preprocessing and VLAN
detection ability
—Offers retry or ignore options following
packet transmission errors
—Supports automatic retransmission following
excessive collisions
—Provides programmable automatic discard of
badly received packets such as runts, CRC
errors, and too long packets
I
Operational
—Enables independent 10 or 100 Mbps port
operation
—Provides full-duplex support
—Enables standard flow-control functionality in
full-duplex mode
—Offers backpressure logic capability in
half-duplex mode
—Interfaces to standard MII connections
—Supports 10BASE-T, 100BASE-TX,
100BASE-T4, and 100BASE-FX connections
—Provides programmable CRC generation and
removal
—Allows backoff limit programming
—Provides full collision support, including
jamming, backoff, and automatic
retransmission
—Complies with IEEE 802.3 Standard
I
CPU Interface
—Supports fully programmable independent
ports through a dedicated generic CPU port
—Enables interrupt programming
I
Device
—Optimized for switch, bridge, and router
applications
—Includes internal and external loopback
capabilities
—Provides software reset support
—Supports JTAG boundary scan
—Low-power 3.3 V and 5 V tolerant CMOS
device
—352-BGA package
Part Number: 278160-005
September, 2000
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